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+ # Copyright (c) 2025 Peter Johanson
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+ # SPDX-License-Identifier: Apache-2.0
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+
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+ description : ST STM32 ROM Bootloader Details
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+
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+ compatible : " st,stm32-bootloader"
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+
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+ include : base.yaml
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+
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+ properties :
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+ reg :
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+ required : true
Original file line number Diff line number Diff line change @@ -38,6 +38,12 @@ config STM32_BACKUP_SRAM_INIT_PRIORITY
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help
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STM32 Backup SRAM device initialization priority.
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+ config STM32_BOOTLOADER
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+ bool "STM32 Bootloader Support"
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+ depends on RETENTION_BOOT_MODE && DT_HAS_ST_STM32_BOOTLOADER_ENABLED
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+ help
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+ Enable support for jumping into the STM32 when the bootmode is set.
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+
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config STM32_ENABLE_DEBUG_SLEEP_STOP
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bool "Allow debugger attach in stop/sleep Mode"
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help
Original file line number Diff line number Diff line change @@ -19,6 +19,8 @@ endif()
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zephyr_sources_ifdef(CONFIG_STM32_BACKUP_SRAM stm32_backup_sram.c)
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zephyr_linker_sources_ifdef(CONFIG_STM32_BACKUP_SRAM SECTIONS stm32_backup_sram.ld)
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+ zephyr_sources_ifdef(CONFIG_STM32_BOOTLOADER stm32_bootloader.c)
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+
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if (NOT CONFIG_DEBUG AND CONFIG_PM)
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zephyr_sources_ifdef(CONFIG_DT_HAS_SWJ_CONNECTOR_ENABLED pm_debug_swj.c)
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endif ()
Original file line number Diff line number Diff line change
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+ /*
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+ * Copyright (c) 2020 Google LLC.
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+ *
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+ * SPDX-License-Identifier: Apache-2.0
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+ */
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+
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+ #include <soc.h>
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+ #include <zephyr/init.h>
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+ #include <zephyr/retention/retention.h>
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+ #include <zephyr/retention/bootmode.h>
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+ #include <stm32_ll_system.h>
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+
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+ static const uint32_t bootloader = DT_REG_ADDR (DT_INST (0 , st_stm32_bootloader ));
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+ static FUNC_NORETURN void jump_to_bootloader (void )
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+ {
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+ int i ;
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+ void (* jmp )(void );
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+
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+ __disable_irq ();
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+
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+ for (i = 0 ; i < ARRAY_SIZE (NVIC -> ICER ); i ++ ) {
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+ NVIC -> ICER [i ] = 0xFFFFFFFF ;
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+ NVIC -> ICPR [i ] = 0xFFFFFFFF ;
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+ }
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+
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+ LL_SYSCFG_SetRemapMemory (LL_SYSCFG_REMAP_SYSTEMFLASH );
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+
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+ jmp = (void (* )(void ))(void (* )(void ))(* ((uint32_t * )((bootloader + 4 ))));
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+
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+ /*
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+ * We need to clear a few things set by the Zephyr early startup code
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+ */
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+ __set_CONTROL (0 );
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+ #if !defined(CONFIG_CPU_CORTEX_M0 )
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+ __set_BASEPRI (0 );
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+ #endif
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+
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+ __set_MSP (* (uint32_t * )bootloader );
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+
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+ __enable_irq ();
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+
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+ jmp ();
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+
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+ CODE_UNREACHABLE ;
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+ }
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+
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+ static int bootloader_check_boot_init (void )
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+ {
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+ if (bootmode_check (BOOT_MODE_TYPE_BOOTLOADER ) > 0 ) {
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+ bootmode_clear ();
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+ jump_to_bootloader ();
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+ }
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+
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+ return 0 ;
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+ }
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+
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+ SYS_INIT (bootloader_check_boot_init , EARLY , 0 );
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