dts: bindings: clock: Fix STM32G4 device clk src selection definitions

Some device clock sources selection helpers were not correctly defined.

With this commit the definitions are updated to match the desciption
in the reference manual RM0453.

Signed-off-by: Thomas Stranger <[email protected]>

Author: str4t0m

include/zephyr/dt-bindings/clock/stm32g4_clock.h

@@ -76,15 +76,15 @@
 #define USART2_SEL(val)		STM32_CLOCK(val, 3, 2, CCIPR_REG)
 #define USART3_SEL(val)		STM32_CLOCK(val, 3, 4, CCIPR_REG)
 #define USART4_SEL(val)		STM32_CLOCK(val, 3, 6, CCIPR_REG)
-#define LPUART1_SEL(val)	STM32_CLOCK(val, 3, 8, CCIPR_REG)
-#define I2C1_SEL(val)		STM32_CLOCK(val, 3, 10, CCIPR_REG)
-#define I2C2_SEL(val)		STM32_CLOCK(val, 3, 12, CCIPR_REG)
-#define I2C3_SEL(val)		STM32_CLOCK(val, 3, 14, CCIPR_REG)
-#define LPTIM1_SEL(val)		STM32_CLOCK(val, 3, 16, CCIPR_REG)
-#define LPTIM2_SEL(val)		STM32_CLOCK(val, 3, 18, CCIPR_REG)
-#define LPTIM3_SEL(val)		STM32_CLOCK(val, 3, 20, CCIPR_REG)
-#define SAI1_SEL(val)		STM32_CLOCK(val, 3, 22, CCIPR_REG)
-#define SAI2_SEL(val)		STM32_CLOCK(val, 3, 24, CCIPR_REG)
+#define USART5_SEL(val)		STM32_CLOCK(val, 3, 8, CCIPR_REG)
+#define LPUART1_SEL(val)	STM32_CLOCK(val, 3, 10, CCIPR_REG)
+#define I2C1_SEL(val)		STM32_CLOCK(val, 3, 12, CCIPR_REG)
+#define I2C2_SEL(val)		STM32_CLOCK(val, 3, 14, CCIPR_REG)
+#define I2C3_SEL(val)		STM32_CLOCK(val, 3, 16, CCIPR_REG)
+#define LPTIM1_SEL(val)		STM32_CLOCK(val, 3, 18, CCIPR_REG)
+#define SAI1_SEL(val)		STM32_CLOCK(val, 3, 20, CCIPR_REG)
+#define I2S23_SEL(val)		STM32_CLOCK(val, 3, 22, CCIPR_REG)
+#define FDCAN_SEL(val)		STM32_CLOCK(val, 3, 24, CCIPR_REG)
 #define CLK48_SEL(val)		STM32_CLOCK(val, 3, 26, CCIPR_REG)
 #define ADC12_SEL(val)		STM32_CLOCK(val, 3, 28, CCIPR_REG)
 #define ADC34_SEL(val)		STM32_CLOCK(val, 3, 30, CCIPR_REG)