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drivers: usb: udc: stm32: accept non-word-aligned MaxPacketSize or FIFOs
STM32 OTG USB controllers use word-addressable RAM with a 32-bit word size so all allocations from the USB SRAM must be 32-bit aligned. The driver did not accept unaligned values of wMaxPacketSize, and FIFO allocation code was implicitly expecting FIFO sizes to be aligned as well (since it allocated "bytes / 4" without rounding up). Update driver to accept values of wMaxPacketSize that aren't word-aligned and to allocate properly sized FIFOs sizes when an unaligned size has been requested. Signed-off-by: Mathieu Choplain <[email protected]>
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drivers/usb/udc/udc_stm32.c

Lines changed: 3 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -652,20 +652,15 @@ static void udc_stm32_mem_init(const struct device *dev)
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653653
LOG_DBG("DRAM size: %ub", cfg->dram_size);
654654

655-
if (cfg->ep_mps % 4) {
656-
LOG_ERR("Not a 32-bit word multiple: ep(%u)", cfg->ep_mps);
657-
return;
658-
}
659-
660655
/* The documentation is not clear at all about RX FiFo size requirement,
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* 160 has been selected through trial and error.
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*/
663-
words = MAX(160, cfg->ep_mps / 4);
658+
words = MAX(160, DIV_ROUND_UP(cfg->ep_mps, 4U));
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HAL_PCDEx_SetRxFiFo(&priv->pcd, words);
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priv->occupied_mem = words * 4;
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667662
/* For EP0 TX, reserve only one MPS */
668-
HAL_PCDEx_SetTxFiFo(&priv->pcd, 0, UDC_STM32_EP0_MAX_PACKET_SIZE / 4);
663+
HAL_PCDEx_SetTxFiFo(&priv->pcd, 0, DIV_ROUND_UP(UDC_STM32_EP0_MAX_PACKET_SIZE, 4U));
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priv->occupied_mem += UDC_STM32_EP0_MAX_PACKET_SIZE;
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/* Reset TX allocs */
@@ -686,7 +681,7 @@ static int udc_stm32_ep_mem_config(const struct device *dev,
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return 0;
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}
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689-
words = MIN(udc_mps_ep_size(ep), cfg->ep_mps) / 4;
684+
words = DIV_ROUND_UP(MIN(udc_mps_ep_size(ep), cfg->ep_mps), 4U);
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words = (words <= 64) ? words * 2 : words;
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if (!enable) {

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