Skip to content

Commit 891aaba

Browse files
benjaminbjornssonbenjaminbjornsson
committed
dts: arm: st: f1: add missing I2S nodes
This commit adds missing I2S nodes for the F1 series. Signed-off-by: Benjamin Björnsson <[email protected]>
1 parent 13b5dc8 commit 891aaba

File tree

4 files changed

+104
-0
lines changed

4 files changed

+104
-0
lines changed

‎dts/arm/st/f1/stm32f103Xe.dtsi‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,5 +18,31 @@
1818
erase-block-size = <DT_SIZE_K(2)>;
1919
};
2020
};
21+
22+
i2s2: i2s@40003800 {
23+
compatible = "st,stm32-i2s";
24+
#address-cells = <1>;
25+
#size-cells = <0>;
26+
reg = <0x40003800 0x400>;
27+
clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
28+
interrupts = <36 5>;
29+
dmas = <&dma1 5 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)
30+
&dma1 4 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>;
31+
dma-names = "tx", "rx";
32+
status = "disabled";
33+
};
34+
35+
i2s3: i2s@40003c00 {
36+
compatible = "st,stm32-i2s";
37+
#address-cells = <1>;
38+
#size-cells = <0>;
39+
reg = <0x40003c00 0x400>;
40+
clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
41+
interrupts = <51 5>;
42+
dmas = <&dma2 2 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)
43+
&dma2 1 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>;
44+
dma-names = "tx", "rx";
45+
status = "disabled";
46+
};
2147
};
2248
};

‎dts/arm/st/f1/stm32f103Xg.dtsi‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,32 @@
2929
};
3030
};
3131

32+
i2s2: i2s@40003800 {
33+
compatible = "st,stm32-i2s";
34+
#address-cells = <1>;
35+
#size-cells = <0>;
36+
reg = <0x40003800 0x400>;
37+
clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
38+
interrupts = <36 5>;
39+
dmas = <&dma1 5 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)
40+
&dma1 4 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>;
41+
dma-names = "tx", "rx";
42+
status = "disabled";
43+
};
44+
45+
i2s3: i2s@40003c00 {
46+
compatible = "st,stm32-i2s";
47+
#address-cells = <1>;
48+
#size-cells = <0>;
49+
reg = <0x40003c00 0x400>;
50+
clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
51+
interrupts = <51 5>;
52+
dmas = <&dma2 2 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)
53+
&dma2 1 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>;
54+
dma-names = "tx", "rx";
55+
status = "disabled";
56+
};
57+
3258
timers9: timers@40014c00 {
3359
compatible = "st,stm32-timers";
3460
reg = <0x40014c00 0x400>;

‎dts/arm/st/f1/stm32f105Xc.dtsi‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,5 +18,31 @@
1818
reg = <0x08000000 DT_SIZE_K(256)>;
1919
};
2020
};
21+
22+
i2s2: i2s@40003800 {
23+
compatible = "st,stm32-i2s";
24+
#address-cells = <1>;
25+
#size-cells = <0>;
26+
reg = <0x40003800 0x400>;
27+
clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
28+
interrupts = <36 5>;
29+
dmas = <&dma1 5 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)
30+
&dma1 4 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>;
31+
dma-names = "tx", "rx";
32+
status = "disabled";
33+
};
34+
35+
i2s3: i2s@40003c00 {
36+
compatible = "st,stm32-i2s";
37+
#address-cells = <1>;
38+
#size-cells = <0>;
39+
reg = <0x40003c00 0x400>;
40+
clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
41+
interrupts = <51 5>;
42+
dmas = <&dma2 2 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)
43+
&dma2 1 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>;
44+
dma-names = "tx", "rx";
45+
status = "disabled";
46+
};
2147
};
2248
};

‎dts/arm/st/f1/stm32f107Xc.dtsi‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,5 +18,31 @@
1818
reg = <0x08000000 DT_SIZE_K(256)>;
1919
};
2020
};
21+
22+
i2s2: i2s@40003800 {
23+
compatible = "st,stm32-i2s";
24+
#address-cells = <1>;
25+
#size-cells = <0>;
26+
reg = <0x40003800 0x400>;
27+
clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
28+
interrupts = <36 5>;
29+
dmas = <&dma1 5 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)
30+
&dma1 4 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>;
31+
dma-names = "tx", "rx";
32+
status = "disabled";
33+
};
34+
35+
i2s3: i2s@40003c00 {
36+
compatible = "st,stm32-i2s";
37+
#address-cells = <1>;
38+
#size-cells = <0>;
39+
reg = <0x40003c00 0x400>;
40+
clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
41+
interrupts = <51 5>;
42+
dmas = <&dma2 2 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)
43+
&dma2 1 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>;
44+
dma-names = "tx", "rx";
45+
status = "disabled";
46+
};
2147
};
2248
};

0 commit comments

Comments
 (0)