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soc: renesas: Add initial support for RA4W1 SOC
Initial commit to support Renesas RA4W1 SOC Signed-off-by: Quy Tran <[email protected]>
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‎dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/clock/ra_clock.h>
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#include <arm/renesas/ra/ra4/ra4-cm4-common.dtsi>
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/ {
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soc {
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(96)>;
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};
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flash-controller@407e0000 {
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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reg = <0x0 DT_SIZE_K(512)>;
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};
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};
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sci4: sci4@40070080 {
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compatible = "renesas,ra-sci";
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interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40070080 0x20>;
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clocks = <&pclka MSTPB 26>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <4>;
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status = "disabled";
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};
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};
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};
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clocks: clocks {
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xtal: clock-xtal {
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compatible = "renesas,ra-cgc-external-clock";
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clock-frequency = <DT_FREQ_M(8)>;
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#clock-cells = <0>;
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status = "disabled";
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};
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hoco: clock-hoco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(48)>;
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#clock-cells = <0>;
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};
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moco: clock-moco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(8)>;
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#clock-cells = <0>;
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};
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loco: clock-loco {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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subclk: clock-subclk {
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compatible = "renesas,ra-cgc-subclk";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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status = "disabled";
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};
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pll: pll {
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compatible = "renesas,ra-cgc-pll";
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#clock-cells = <0>;
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/* PLL */
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source = <RA_PLL_SOURCE_MAIN_OSC>;
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div = <RA_PLL_DIV_2>;
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mul = <12 0>;
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freq = <DT_FREQ_M(48)>;
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status = "disabled";
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};
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pclkblock: pclkblock {
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compatible = "renesas,ra-cgc-pclk-block";
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#clock-cells = <0>;
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sysclock-src = <RA_CLOCK_SOURCE_HOCO>;
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status = "okay";
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iclk: iclk {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_1>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclka: pclka {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_1>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkb: pclkb {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_2>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkc: pclkc {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_1>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkd: pclkd {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_1>;
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#clock-cells = <2>;
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status = "okay";
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};
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fclk: fclk {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_2>;
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#clock-cells = <2>;
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status = "okay";
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};
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clkout: clkout {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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uclk: uclk {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_USB_CLOCK_DIV_1>;
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#clock-cells = <2>;
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status = "okay";
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};
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};
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};
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};

‎dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
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#include <freq.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m4";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv7m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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};
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soc {
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system: system@4001e000 {
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compatible = "renesas,ra-system";
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reg = <0x4001e000 0x1000>;
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status = "okay";
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};
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flash-controller@407e0000 {
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reg = <0x407e0000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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ioport0: gpio@40040000 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40040000 0x20>;
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port = <0>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport1: gpio@40040020 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40040020 0x20>;
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port = <1>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport2: gpio@40040040 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40040040 0x20>;
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port = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport3: gpio@40040060 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40040060 0x20>;
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port = <3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport4: gpio@40040080 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40040080 0x20>;
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port = <4>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport5: gpio@400400a0 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x400400a0 0x20>;
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port = <5>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport9: gpio@40040120 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40040120 0x20>;
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port = <9>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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pinctrl: pin-controller@40040800 {
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compatible = "renesas,ra-pinctrl-pfs";
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reg = <0x40040800 0x3c0>;
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status = "okay";
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};
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sci0: sci0@40070000 {
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compatible = "renesas,ra-sci";
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interrupts = <0 1>, <1 1>, <2 1>, <3 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40070000 0x20>;
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clocks = <&pclka MSTPB 31>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <0>;
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status = "disabled";
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};
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};
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sci1: sci1@40070020 {
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compatible = "renesas,ra-sci";
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interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40070020 0x20>;
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clocks = <&pclka MSTPB 30>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <1>;
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status = "disabled";
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};
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};
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sci9: sci9@40070120 {
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compatible = "renesas,ra-sci";
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interrupts = <36 1>, <37 1>, <38 1>, <39 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40070120 0x20>;
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clocks = <&pclka MSTPB 22>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <9>;
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status = "disabled";
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};
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};
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id_code: id_code@1010018 {
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compatible = "zephyr,memory-region";
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reg = <0x01010018 0x20>;
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zephyr,memory-region = "ID_CODE";
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status = "okay";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};

‎soc/renesas/ra/ra4w1/CMakeLists.txt‎

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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zephyr_include_directories(.)
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zephyr_sources(
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soc.c
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)
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zephyr_linker_sources(ROM_START opt_set_mem.ld)
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zephyr_linker_sources(SECTIONS sections.ld)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

‎soc/renesas/ra/ra4w1/Kconfig‎

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RA4W1
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select ARM
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select CPU_HAS_ARM_MPU
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select CPU_CORTEX_M4
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select HAS_RENESAS_RA_FSP
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_FPU
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select FPU
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select HAS_SWO
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select XIP

‎soc/renesas/ra/ra4w1/Kconfig.defconfig‎

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_RA4W1
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config NUM_IRQS
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default 32
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config PINCTRL
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default y
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endif # SOC_SERIES_RA4W1

‎soc/renesas/ra/ra4w1/Kconfig.soc‎

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RA4W1
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bool
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select SOC_FAMILY_RENESAS_RA
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help
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Renesas RA4W1 series
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config SOC_R7FA4W1AD2CNG
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bool
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select SOC_SERIES_RA4W1
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help
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R7FA4W1AD2CNG
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config SOC_SERIES
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default "ra4w1" if SOC_SERIES_RA4W1
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config SOC
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default "r7fa4w1ad2cng" if SOC_R7FA4W1AD2CNG

‎soc/renesas/ra/ra4w1/opt_set_mem.ld‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* ROM Registers start at address 0x00000400 */
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. = 0x400;
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KEEP(*(.rom_registers*))
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/* Reserving 0x100 bytes of space for ROM registers. */
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. = 0x500;

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