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ParthibanI17164cfriedt
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drivers: ethernet: phy: microchip_t1s: fix missing MDIO bus enable/disable
Call mdio_bus_enable() and mdio_bus_disable() during clause 22 register read/write operations. Previously, these APIs were not invoked, which could lead to improper MDIO bus handling. This issue was observed during testing with the evb-lan8670-rmii (an external LAN8670 PHY) connected to the SAME54 Curiosity Ultra platform. Signed-off-by: Parthiban Veerasooran <[email protected]>
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drivers/ethernet/phy/phy_microchip_t1s.c

Lines changed: 32 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -107,18 +107,32 @@ struct mc_t1s_data {
107107
static int phy_mc_t1s_read(const struct device *dev, uint16_t reg, uint32_t *data)
108108
{
109109
const struct mc_t1s_config *cfg = dev->config;
110+
int ret;
110111

111112
/* Make sure excessive bits 16-31 are reset */
112113
*data = 0U;
113114

114-
return mdio_read(cfg->mdio, cfg->phy_addr, reg, (uint16_t *)data);
115+
mdio_bus_enable(cfg->mdio);
116+
117+
ret = mdio_read(cfg->mdio, cfg->phy_addr, reg, (uint16_t *)data);
118+
119+
mdio_bus_disable(cfg->mdio);
120+
121+
return ret;
115122
}
116123

117124
static int phy_mc_t1s_write(const struct device *dev, uint16_t reg, uint32_t data)
118125
{
119126
const struct mc_t1s_config *cfg = dev->config;
127+
int ret;
128+
129+
mdio_bus_enable(cfg->mdio);
130+
131+
ret = mdio_write(cfg->mdio, cfg->phy_addr, reg, (uint16_t)data);
120132

121-
return mdio_write(cfg->mdio, cfg->phy_addr, reg, (uint16_t)data);
133+
mdio_bus_disable(cfg->mdio);
134+
135+
return ret;
122136
}
123137

124138
static int mdio_setup_c45_indirect_access(const struct device *dev, uint16_t devad, uint16_t reg)
@@ -150,13 +164,20 @@ static int phy_mc_t1s_c45_read(const struct device *dev, uint8_t devad, uint16_t
150164
return mdio_read_c45(cfg->mdio, cfg->phy_addr, devad, reg, val);
151165
}
152166

167+
mdio_bus_enable(cfg->mdio);
168+
153169
/* Read C45 registers using C22 indirect access registers */
154170
ret = mdio_setup_c45_indirect_access(dev, devad, reg);
155171
if (ret) {
172+
mdio_bus_disable(cfg->mdio);
156173
return ret;
157174
}
158175

159-
return mdio_read(cfg->mdio, cfg->phy_addr, MII_MMD_AADR, val);
176+
ret = mdio_read(cfg->mdio, cfg->phy_addr, MII_MMD_AADR, val);
177+
178+
mdio_bus_disable(cfg->mdio);
179+
180+
return ret;
160181
}
161182

162183
static int phy_mc_t1s_c45_write(const struct device *dev, uint8_t devad, uint16_t reg, uint16_t val)
@@ -170,13 +191,20 @@ static int phy_mc_t1s_c45_write(const struct device *dev, uint8_t devad, uint16_
170191
return mdio_write_c45(cfg->mdio, cfg->phy_addr, devad, reg, val);
171192
}
172193

194+
mdio_bus_enable(cfg->mdio);
195+
173196
/* Write C45 registers using C22 indirect access registers */
174197
ret = mdio_setup_c45_indirect_access(dev, devad, reg);
175198
if (ret) {
199+
mdio_bus_disable(cfg->mdio);
176200
return ret;
177201
}
178202

179-
return mdio_write(cfg->mdio, cfg->phy_addr, MII_MMD_AADR, val);
203+
ret = mdio_write(cfg->mdio, cfg->phy_addr, MII_MMD_AADR, val);
204+
205+
mdio_bus_disable(cfg->mdio);
206+
207+
return ret;
180208
}
181209

182210
static int phy_mc_t1s_get_link(const struct device *dev, struct phy_link_state *state)

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