dts: renesas: Add flash support for RZ/A3UL, N2L, T2M

Add SPIBSC node for RZ/A3UL
Add XSPI node for RZ/T2M, N2L

Signed-off-by: Tien Nguyen <[email protected]>

Author: tiennguyenzg

dts/arm/renesas/rz/rzn/r9a07g084.dtsi

@@ -1266,5 +1266,25 @@
 			interrupts = <GIC_SPI 388 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
 			status = "disabled";
 		};
+
+		xspi0: xspi@80220000 {
+			compatible = "renesas,rz-xspi";
+			reg = <0x80220000 0x1000>;
+			interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_SPI 340 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "disabled";
+		};
+
+		xspi1: xspi@80221000 {
+			compatible = "renesas,rz-xspi";
+			reg = <0x80221000 0x1000>;
+			interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_SPI 342 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "disabled";
+		};
 	};
 };

dts/arm/renesas/rz/rzt/r9a07g075.dtsi

@@ -1270,5 +1270,26 @@
 			interrupts = <GIC_SPI 388 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
 			status = "disabled";
 		};
+
+		xspi0: xspi@80220000 {
+			compatible = "renesas,rz-xspi";
+			reg = <0x80220000 0x1000>;
+			interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_SPI 340 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "disabled";
+		};
+
+		xspi1: xspi@80221000 {
+			compatible = "renesas,rz-xspi";
+			reg = <0x80221000 0x1000>;
+			interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_SPI 342 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "disabled";
+		};
+
 	};
 };

dts/arm64/renesas/rz/rza/r9a07g063.dtsi

@@ -919,5 +919,14 @@
 			clock-freq = <DT_FREQ_M(24)>;
 			status = "disabled";
 		};
+
+		spibsc: spibsc@10060000 {
+			compatible = "renesas,rz-spibsc";
+			reg = <0x10060000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "disabled";
+		};
+
 	};
 };