arch: arm: cortex_a_r: smp: minor fix for non cache coherent cores

What is changed?
1. Updated the data sync barrier to make sure the other parameters of
   `arm_cpu_boot_params` are updated before updating its member `mpidr`
2. Updated the MPIDR affinity level mask to account for affinity level
   1 and 2 along with level 0.

Why do we need this change?
1. As reported in issue #76182, on Cortex_A_R, the current code
   execution fails to consider the correct sequence of data sync
   barrier and cache maintenece for the code to work on non cache
   coherent cores in SMP enabled mode.
   The secondary cores are waiting in a loop for primary core to set
   `arm_cpu_boot_params.mpidr`. As soon as primary core set this,
    the secondary cores start reading other parameters from the
   `arm_cpu_boot_params` however, the existing position of DSB
   instruction doesn't guarantee that `arg`, `cpu_num` and other
   parameters of `arm_cpu_boot_params` would be updated before `mpidr`
   is udpated and this could lead to a unpredicatble behaviour so,
   we need to move the DSB instruction.
2. The affinity level mask is updated because it didn't account for
   level 1 to identify individual cores within a cluster and
   level 2 to identify different clusters within the system which can
   lead to an incorrect conversion between mpidr to core-id.

Signed-off-by: Sudan Landge <[email protected]>

Author: wearyzen

arch/arm/core/cortex_a_r/smp.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved.
+ * Copyright (c) 2023, 2024 Arm Limited (or its affiliates).
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -139,10 +139,14 @@ void arch_cpu_start(int cpu_num, k_thread_stack_t *stack, int sz, arch_cpustart_
 	arm_cpu_boot_params.arg = arg;
 	arm_cpu_boot_params.cpu_num = cpu_num;
 
+	/* we need the barrier here to make sure the above changes to
+	 * arm_cpu_boot_params are completed before we set the mpid
+	 */
+	barrier_dsync_fence_full();
+
 	/* store mpid last as this is our synchronization point */
 	arm_cpu_boot_params.mpid = cpu_mpid;
 
-	barrier_dsync_fence_full();
 	sys_cache_data_invd_range(
 			(void *)&arm_cpu_boot_params,
 			sizeof(arm_cpu_boot_params));

include/zephyr/arch/arm/cortex_a_r/cpu.h

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018 Lexmark International, Inc.
+ * Copyright 2024 Arm Limited and/or its affiliates <[email protected]>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -84,8 +85,8 @@
 #define ICC_SRE_ELx_DIB_BIT	BIT(2)
 #define ICC_SRE_EL3_EN_BIT	BIT(3)
 
-/* MPIDR */
-#define MPIDR_AFFLVL_MASK	(0xff)
+/* MPIDR mask to extract Aff0, Aff1, and Aff2 */
+#define MPIDR_AFFLVL_MASK (0xffffff)
 
 #define MPIDR_AFF0_SHIFT	(0)
 #define MPIDR_AFF1_SHIFT	(8)