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boards: imx943_evk: add i.MX 943 EVK board support for A55
The IMX943 EVK board is a design and evaluation platform based on the NXP i.MX 943 processor. Signed-off-by: Jiafei Pan <[email protected]>
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‎boards/nxp/imx943_evk/Kconfig.defconfig‎

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# Copyright 2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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config INTC_INIT_PRIORITY
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default 2
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config MBOX_INIT_PRIORITY
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default 3

‎boards/nxp/imx943_evk/Kconfig.imx943_evk‎

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# Copyright 2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_IMX943_EVK
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select SOC_MIMX94398_A55 if BOARD_IMX943_EVK_MIMX94398_A55
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select SOC_PART_NUMBER_MIMX94398AVKM

‎boards/nxp/imx943_evk/board.yml‎

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board:
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name: imx943_evk
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full_name: i.MX943 EVK
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vendor: nxp
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socs:
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- name: mimx94398

‎boards/nxp/imx943_evk/doc/index.rst‎

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.. zephyr:board:: imx943_evk
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Overview
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********
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The IMX943LP5EVK-19 board is a design and evaluation platform based on the
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NXP i.MX 943 processor. The i.MX 943 processor integrates up to four Arm
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Cortex-A55 cores, along with two Arm Cortex-M33 cores and two Arm Cortex-M7
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cores for functional safety. With PLCs, I/O controllers, V2X accelerators,
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ML acceleration, energy management, and advanced security, the i.MX 943
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processor provides optimized performance and power efficiency for industrial,
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IoT, and automotive devices. The i.MX943 device on the board comes in a
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compact 19 x 19 mm package.
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Hardware
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********
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- i.MX 943 automotive applications processor
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- The processor integrates up to four Arm Cortex-A55 cores, and supports
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functional safety with built-in Arm Cortex-M33 and -M7 cores
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- DRAM memory: 8-Gbit LPDDR5 DRAM
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- XSPI interface: 64 MB octal SPI NOR flash memory
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- eMMC: 32 GB eMMC NAND flash memory
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- uSDHC interface: an SD card slot
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- USB interface: Two USB Type-C ports
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- Ethernet interface: seven Ethernet ports
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- PCIe interface: one M.2 slot and one PCIe x4 slot.
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- FlexCAN interface: four CAN controller with four CAN connector.
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- LPUART interface
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- LPSPI interface
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- LPI2C interface
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- SAI interface
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- MQS interface
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- MICFIL interface
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- LVDS interface
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- ADC interface
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- SINC interface
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- Debug interface
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- One USB-to-UART/MPSSE device, FT4232H
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- One USB 3.2 Type-C connector (J15) for FT4232H provides quad serial ports
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- JTAG header J16
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Supported Features
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==================
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.. zephyr:board-supported-hw::
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System Clock
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------------
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This board configuration uses a system clock frequency of 24 MHz for Cortex-A55.
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Cortex-A55 Core runs up to 1.7 GHz.
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Serial Port
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-----------
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This board configuration uses a single serial communication channel with the
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CPU's UART1 for Cortex-A55.
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Programming and Debugging (A55)
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*******************************
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.. zephyr:board-supported-runners::
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Boot Zephyr by Using U-Boot Command
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===================================
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U-Boot "go" command can be used to start Zephyr on A55 Core0.
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Dependency
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----------
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Need to disable all watchdog in U-Boot, otherwise, watchdog will reset the board
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after Zephyr start up from the same A55 Core.
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Step 1: Build Zephyr application
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--------------------------------
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Here is an example for the :zephyr:code-sample:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:host-os: unix
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:board: imx943_evk/mimx94398/a55
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:goals: build
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Step 2: Download Zephyr Image into DDR Memory
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---------------------------------------------
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Firstly need to download Zephyr binary image into DDR memory, it can use tftp:
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.. code-block:: console
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tftp 0xd0000000 zephyr.bin
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Or copy the Zephyr image ``zephyr.bin`` SD card and plug the card into the board, for example
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if copy to the FAT partition of the SD card, use the following U-Boot command to load the image
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into DDR memory (assuming the SD card is dev 1, fat partition ID is 1, they could be changed
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based on actual setup):
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.. code-block:: console
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fatload mmc 1:1 0xd0000000 zephyr.bin;
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Step 3: Boot Zephyr
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-------------------
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Use the following command to boot Zephyr on the core0:
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.. code-block:: console
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dcache off; icache flush; go 0xd0000000;
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Then the following log could be found on UART1 console:
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.. code-block:: console
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*** Booting Zephyr OS build v4.1.0-3650-gdb71736adb68 ***
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Hello World! imx943_evk/mimx94398/a55
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.. include:: ../../common/board-footer.rst
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:start-after: nxp-board-footer

‎boards/nxp/imx943_evk/imx943_evk-pinctrl.dtsi‎

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/*
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* Copyright 2025 NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <nxp/nxp_imx/mimx94398avkm-pinctrl.dtsi>
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&pinctrl {
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lpuart1_default: lpuart1_default {
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group0 {
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pinmux = <&iomuxc_uart1_rxd_lpuart_rx_lpuart1_rx>,
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<&iomuxc_uart1_txd_lpuart_tx_lpuart1_tx>;
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bias-pull-up;
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slew-rate = "slightly_fast";
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drive-strength = "x4";
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};
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};
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};

‎boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.dts‎

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/*
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* Copyright 2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <nxp/nxp_mimx943_a55.dtsi>
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#include "imx943_evk-pinctrl.dtsi"
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/ {
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model = "NXP i.MX943 A55";
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compatible = "fsl,mimx943";
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chosen {
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zephyr,console = &lpuart1;
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zephyr,shell-uart = &lpuart1;
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/* sram node actually locates at DDR DRAM */
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zephyr,sram = &dram;
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};
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cpus {
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cpu@0 {
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status = "disabled";
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};
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cpu@100 {
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status = "disabled";
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};
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cpu@200 {
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status = "disabled";
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};
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};
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dram: memory@d0000000 {
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reg = <0xd0000000 DT_SIZE_M(1)>;
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};
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};
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&lpuart1 {
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status = "okay";
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current-speed = <115200>;
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pinctrl-0 = <&lpuart1_default>;
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pinctrl-names = "default";
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};

‎boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.yaml‎

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#
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# Copyright 2025 NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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identifier: imx943_evk/mimx94398/a55
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name: NXP i.MX943 EVK A55
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type: mcu
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arch: arm64
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toolchain:
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- zephyr
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- cross-compile
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ram: 1024
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supported:
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- uart
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vendor: nxp

‎boards/nxp/imx943_evk/imx943_evk_mimx94398_a55_defconfig‎

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#
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# Copyright 2025 NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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# ARM Options
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CONFIG_AARCH64_IMAGE_HEADER=y
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CONFIG_ARMV8_A_NS=y
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# MMU Options
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CONFIG_MAX_XLAT_TABLES=24
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# Cache Options
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CONFIG_CACHE_MANAGEMENT=y
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CONFIG_DCACHE_LINE_SIZE_DETECT=y
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CONFIG_ICACHE_LINE_SIZE_DETECT=y
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# Zephyr Kernel Configuration
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CONFIG_XIP=n
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CONFIG_KERNEL_DIRECT_MAP=y
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# Serial Drivers
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CONFIG_SERIAL=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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# Enable Console
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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CONFIG_CLOCK_CONTROL=y
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CONFIG_MBOX=y
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CONFIG_ARM_SCMI=y

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