rp2350: Define and implement a cpucluster of Cortex-M33s

Assume that users want to run a dual Cortex-M33 on the Pico 2, and
update various parts of the codebase to match. I expect the majority of
the soc's definition will move from `dts/arm/raspberrypi` to
`dts/common/raspberrypi` if/when support is added for the Hazard3 cores.

Some parts of the codebase can cope without encoding the cluster in the
filename (e.g. Twister seems to use the identifier in
`boards/raspberrypi/rpi_pico2/rpi_pico2.yaml` rather than the filename
itself), others can't (e.g. `rpi_pico2_m33_defconfig`) which itself is
a form of <board>_<cpucluster>_defconfig and doesn't refer to the SoC.
Despite this, some files have been given the verbose fully-specified
name because this matches the current documentation.

Update documentation to try to highlight the capabilities and
limitations of the current support within Zephyr for the Pico 2 board
and the underlying SoC.

Update `.overlay` and `.conf` files in `samples/` and `tests/` to match
the new requirement.

Limited tested locally with no issues found.

Signed-off-by: Andrew Featherstone <[email protected]>

Author: ajf58

boards/raspberrypi/rpi_pico2/Kconfig.rpi_pico2

@@ -2,4 +2,4 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_RPI_PICO2
-	select SOC_RP2350A
+	select SOC_RP2350A_M33 if BOARD_RPI_PICO2_RP2350A_M33

boards/raspberrypi/rpi_pico2/doc/index.rst

@@ -6,6 +6,10 @@ Overview
 The Raspberry Pi Pico 2 is the second-generation product in the Raspberry Pi
 Pico family. From the `Raspberry Pi website <https://www.raspberrypi.com/documentation/microcontrollers/pico-series.html>`_ is referred to as Pico 2.
 
+There are many limitations of the board currently. Including but not limited to:
+- The Zephyr build only supports configuring the RP2350A with the Cortex-M33 cores.
+- As with the Pico 1, there's no support for running any code on the second core.
+
 Hardware
 ********
 
@@ -26,7 +30,7 @@ Hardware
 Supported Features
 ==================
 
-The ``rpi_pico2`` board target supports the following
+The ``rpi_pico2/rp2350a/m33`` board target supports the following
 hardware features:
 
 .. list-table::

boards/raspberrypi/rpi_pico2/rpi_pico2.dts renamed to boards/raspberrypi/rpi_pico2/rpi_pico2.dtsi

@@ -4,15 +4,11 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-/dts-v1/;
-
 #include <freq.h>
 
 #include <zephyr/dt-bindings/i2c/i2c.h>
 #include <zephyr/dt-bindings/pwm/pwm.h>
 
-#include <raspberrypi/rpi_pico/rp2350a.dtsi>
-
 #include "rpi_pico2-pinctrl.dtsi"
 #include "../common/rpi_pico-led.dtsi"
 

boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.dts

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024 Andrew Featherstone
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+/* The build system assumes that there's a cpucluster-specific file.
+ *
+ * This file provides composition of the device tree:
+ * 1. The common features of the SoC
+ * 2. Core-specific configuration.
+ * 3. Board-specific configuration.
+ */
+#include <raspberrypi/rpi_pico/rp2350a.dtsi>
+#include <raspberrypi/rpi_pico/m33.dtsi>
+
+/* there's nothing specific to the Cortex-M33 cores vs the (not yet
+ * implemented) Hazard3 cores.
+ */
+#include "rpi_pico2.dtsi"

boards/raspberrypi/rpi_pico2/rpi_pico2.yaml renamed to boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.yaml

@@ -1,5 +1,5 @@
-identifier: rpi_pico2
-name: Raspberry Pi Pico 2
+identifier: rpi_pico2/rp2350a/m33
+name: Raspberry Pi Pico 2 (Cortex-M33)
 type: mcu
 arch: arm
 flash: 4096

boards/raspberrypi/rpi_pico2/rpi_pico2_defconfig renamed to boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_defconfig

@@ -1,3 +1,6 @@
+# This configuration is orthogonal to whether the Cortex-M33 or Hazard3 cores
+# are in use, but Zephyr does not support providing a qualifier-agnostic
+# _defconfig file.
 CONFIG_BUILD_OUTPUT_HEX=y
 CONFIG_BUILD_OUTPUT_UF2=y
 CONFIG_CLOCK_CONTROL=y

dts/arm/raspberrypi/rpi_pico/m33.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024 Andrew Featherstone
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv8-m.dtsi>
+
+/* Model in the device tree a Cortex-M33 core being 'plugged' into each
+ * 'socket' within the SoC. Within the datasheet these are core 0 and core 1.
+ */
+&cpu0 {
+	compatible = "arm,cortex-m33";
+};
+
+&cpu1 {
+	compatible = "arm,cortex-m33";
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};

dts/arm/raspberrypi/rpi_pico/rp2350.dtsi

@@ -4,7 +4,6 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <arm/armv8-m.dtsi>
 #include <zephyr/dt-bindings/adc/adc.h>
 #include <zephyr/dt-bindings/gpio/gpio.h>
 #include <zephyr/dt-bindings/clock/rpi_pico_rp2350_clock.h>
@@ -26,13 +25,16 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		/* There are two CPU sockets in the RP2350-series SoCs.
+		 * Represent the sockets in the device tree as these two
+		 * partially-defined CPU instances. Use a separate DTSI file to
+		 * define what kind of CPU cores they are.
+		 */
 		cpu0: cpu@0 {
-			compatible = "arm,cortex-m33";
 			reg = <0>;
 		};
 
 		cpu1: cpu@1 {
-			compatible = "arm,cortex-m33";
 			reg = <1>;
 		};
 	};
@@ -434,7 +436,3 @@
 		status = "disabled";
 	};
 };
-
-&nvic {
-	arm,num-irq-priority-bits = <4>;
-};