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lgl88911MaureenHelm
lgl88911
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MaureenHelm
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boards: mm_swiftio: modify to follow code style
Move the unrelated whitespace and Modify line break alignment. Signed-off-by: Frank Li <[email protected]>
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‎boards/arm/mm_swiftio/pinmux.c

Lines changed: 48 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -20,30 +20,30 @@ static gpio_pin_config_t enet_gpio_config = {
2020
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_ACCESS_USDHC1
2121

2222
/*Drive Strength Field: R0(260 Ohm @ 3.3V, 150 [email protected], 240 Ohm for DDR)
23-
*Speed Field: medium(100MHz)
24-
*Open Drain Enable Field: Open Drain Disabled
25-
*Pull / Keep Enable Field: Pull/Keeper Enabled
26-
*Pull / Keep Select Field: Pull
27-
*Pull Up / Down Config. Field: 47K Ohm Pull Up
28-
*Hyst. Enable Field: Hysteresis Enabled.
23+
* Speed Field: medium(100MHz)
24+
* Open Drain Enable Field: Open Drain Disabled
25+
* Pull / Keep Enable Field: Pull/Keeper Enabled
26+
* Pull / Keep Select Field: Pull
27+
* Pull Up / Down Config. Field: 47K Ohm Pull Up
28+
* Hyst. Enable Field: Hysteresis Enabled.
2929
*/
3030

3131
static void mm_swiftio_usdhc_pinmux(
3232
uint16_t nusdhc, bool init,
3333
uint32_t speed, uint32_t strength)
3434
{
3535
uint32_t cmd_data = IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) |
36-
IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
37-
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
38-
IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
39-
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
40-
IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
41-
IOMUXC_SW_PAD_CTL_PAD_DSE(strength);
36+
IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
37+
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
38+
IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
39+
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
40+
IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
41+
IOMUXC_SW_PAD_CTL_PAD_DSE(strength);
4242
uint32_t clk = IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) |
43-
IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
44-
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
45-
IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
46-
IOMUXC_SW_PAD_CTL_PAD_DSE(strength);
43+
IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
44+
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
45+
IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
46+
IOMUXC_SW_PAD_CTL_PAD_DSE(strength);
4747

4848
if (nusdhc == 0) {
4949
if (init) {
@@ -87,17 +87,17 @@ static void mm_swiftio_usdhc_pinmux(
8787
}
8888

8989
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD,
90-
cmd_data);
90+
cmd_data);
9191
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK,
92-
clk);
92+
clk);
9393
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0,
94-
cmd_data);
94+
cmd_data);
9595
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1,
96-
cmd_data);
96+
cmd_data);
9797
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2,
98-
cmd_data);
98+
cmd_data);
9999
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,
100-
cmd_data);
100+
cmd_data);
101101
}
102102
}
103103
#endif
@@ -150,41 +150,41 @@ static int mm_swiftio_init(const struct device *dev)
150150
#endif
151151

152152
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c1), okay) && CONFIG_I2C
153-
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 1);
154-
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 1);
155-
156-
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL,
157-
IOMUXC_SW_PAD_CTL_PAD_PUS(3) |
158-
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
159-
IOMUXC_SW_PAD_CTL_PAD_ODE_MASK |
160-
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
161-
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
162-
163-
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA,
164-
IOMUXC_SW_PAD_CTL_PAD_PUS(3) |
165-
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
166-
IOMUXC_SW_PAD_CTL_PAD_ODE_MASK |
167-
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
168-
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
153+
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 1);
154+
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 1);
155+
156+
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL,
157+
IOMUXC_SW_PAD_CTL_PAD_PUS(3) |
158+
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
159+
IOMUXC_SW_PAD_CTL_PAD_ODE_MASK |
160+
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
161+
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
162+
163+
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA,
164+
IOMUXC_SW_PAD_CTL_PAD_PUS(3) |
165+
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
166+
IOMUXC_SW_PAD_CTL_PAD_ODE_MASK |
167+
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
168+
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
169169
#endif
170170

171171
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c3), okay) && CONFIG_I2C
172172
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL, 1);
173173
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA, 1);
174174

175175
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL,
176-
IOMUXC_SW_PAD_CTL_PAD_PUS(3) |
177-
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
178-
IOMUXC_SW_PAD_CTL_PAD_ODE_MASK |
179-
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
180-
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
176+
IOMUXC_SW_PAD_CTL_PAD_PUS(3) |
177+
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
178+
IOMUXC_SW_PAD_CTL_PAD_ODE_MASK |
179+
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
180+
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
181181

182182
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA,
183-
IOMUXC_SW_PAD_CTL_PAD_PUS(3) |
184-
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
185-
IOMUXC_SW_PAD_CTL_PAD_ODE_MASK |
186-
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
187-
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
183+
IOMUXC_SW_PAD_CTL_PAD_PUS(3) |
184+
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
185+
IOMUXC_SW_PAD_CTL_PAD_ODE_MASK |
186+
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
187+
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
188188
#endif
189189

190190
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_ACCESS_USDHC1

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