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JhanBoChao-Realtekkartben
JhanBoChao-Realtek
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kartben
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driver: espi: add espi peripheral channel HOST_CMD driver for rts5912
espi: add espi peripheral channel HOST_CMD driver for rts5912 Unlike other chips using IO port 0x800-0x8ff, we utilize shared memory to transfer host command parameters. The AP firmware must have corresponding settings for this configuration. Signed-off-by: jhan bo chao <[email protected]>
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‎drivers/espi/Kconfig.rts5912

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Original file line numberDiff line numberDiff line change
@@ -10,6 +10,9 @@ config ESPI_RTS5912
1010

1111
if ESPI_RTS5912
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config ESPI_PERIPHERAL_EC_HOST_CMD
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default y
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config ESPI_PERIPHERAL_DEBUG_PORT_80
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default y
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‎drivers/espi/espi_realtek_rts5912.c

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Original file line numberDiff line numberDiff line change
@@ -17,6 +17,8 @@
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LOG_MODULE_REGISTER(espi, CONFIG_ESPI_LOG_LEVEL);
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#include "espi_utils.h"
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#include "reg/reg_acpi.h"
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#include "reg/reg_emi.h"
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#include "reg/reg_espi.h"
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#include "reg/reg_port80.h"
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@@ -26,6 +28,14 @@ struct espi_rts5912_config {
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volatile struct espi_reg *const espi_reg;
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uint32_t espislv_clk_grp;
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uint32_t espislv_clk_idx;
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#ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
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volatile struct acpi_reg *const promt0_reg;
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uint32_t promt0_clk_grp;
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uint32_t promt0_clk_idx;
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volatile struct emi_reg *const emi0_reg;
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uint32_t emi0_clk_grp;
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uint32_t emi0_clk_idx;
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#endif
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#ifdef CONFIG_ESPI_PERIPHERAL_DEBUG_PORT_80
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volatile struct port80_reg *const port80_reg;
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uint32_t port80_clk_grp;
@@ -51,6 +61,88 @@ struct espi_rts5912_data {
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#endif
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};
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/*
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* =========================================================================
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* ESPI Peripheral EC Host Command (Promt0)
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* =========================================================================
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*/
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#ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
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#define ESPI_RTK_PERIPHERAL_HOST_CMD_PARAM_SIZE 256
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static uint8_t ec_host_cmd_sram[ESPI_RTK_PERIPHERAL_HOST_CMD_PARAM_SIZE] __aligned(256);
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static void espi_setup_host_cmd_shm(const struct espi_rts5912_config *const espi_config)
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{
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volatile struct emi_reg *const emi0_reg = espi_config->emi0_reg;
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emi0_reg->SAR = (uint32_t)&ec_host_cmd_sram[0];
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}
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static void promt0_ibf_isr(const struct device *dev)
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{
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const struct espi_rts5912_config *const espi_config = dev->config;
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volatile struct acpi_reg *const promt0_reg = espi_config->promt0_reg;
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struct espi_rts5912_data *data = dev->data;
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struct espi_event evt = {.evt_type = ESPI_BUS_PERIPHERAL_NOTIFICATION,
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.evt_details = ESPI_PERIPHERAL_EC_HOST_CMD,
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.evt_data = ESPI_PERIPHERAL_NODATA};
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promt0_reg->STS |= ACPI_STS_STS0;
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evt.evt_data = (uint8_t)promt0_reg->IB;
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espi_send_callbacks(&data->callbacks, dev, evt);
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}
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static int espi_promt0_setup(const struct device *dev)
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{
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const struct espi_rts5912_config *const espi_config = dev->config;
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struct rts5912_sccon_subsys sccon;
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volatile struct acpi_reg *const promt0_reg = espi_config->promt0_reg;
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int rc;
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if (!device_is_ready(espi_config->clk_dev)) {
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LOG_ERR("Promt0 clock not ready");
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return -ENODEV;
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}
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sccon.clk_grp = espi_config->promt0_clk_grp;
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sccon.clk_idx = espi_config->promt0_clk_idx;
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rc = clock_control_on(espi_config->clk_dev, (clock_control_subsys_t)&sccon);
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if (rc != 0) {
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LOG_ERR("Promt0 clock control on failed");
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return rc;
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}
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promt0_reg->STS = 0;
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if (promt0_reg->STS & ACPI_STS_IBF) {
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rc = promt0_reg->IB;
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}
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if (promt0_reg->STS & ACPI_STS_IBF) {
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promt0_reg->IB |= ACPI_IB_IBCLR;
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}
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promt0_reg->PTADDR =
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CONFIG_ESPI_PERIPHERAL_HOST_CMD_DATA_PORT_NUM | (0x04 << ACPI_PTADDR_OFFSET_Pos);
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promt0_reg->VWCTRL1 = ACPI_VWCTRL1_ACTEN;
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promt0_reg->INTEN = ACPI_INTEN_IBFINTEN;
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NVIC_ClearPendingIRQ(DT_IRQ_BY_NAME(DT_DRV_INST(0), promt0_ibf, irq));
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/* IBF */
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IRQ_CONNECT(DT_IRQ_BY_NAME(DT_DRV_INST(0), promt0_ibf, irq),
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DT_IRQ_BY_NAME(DT_DRV_INST(0), promt0_ibf, priority), promt0_ibf_isr,
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DEVICE_DT_GET(DT_DRV_INST(0)), 0);
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irq_enable(DT_IRQ_BY_NAME(DT_DRV_INST(0), promt0_ibf, irq));
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return 0;
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}
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#endif /* CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD */
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/*
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* =========================================================================
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* ESPI Peripheral Debug Port 80
@@ -1635,6 +1727,16 @@ static int espi_rts5912_init(const struct device *dev)
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/* Setup eSPI bus reset */
16361728
espi_bus_reset_setup(dev);
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#ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
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rc = espi_promt0_setup(dev);
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if (rc != 0) {
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LOG_ERR("eSPI Promt0 setup failed");
1734+
goto exit;
1735+
}
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espi_setup_host_cmd_shm(espi_config);
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#endif
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#ifdef CONFIG_ESPI_PERIPHERAL_DEBUG_PORT_80
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/* Setup Port80 */
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rc = espi_peri_ch_port80_setup(dev);
@@ -1679,6 +1781,15 @@ static const struct espi_rts5912_config espi_rts5912_config = {
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.espi_reg = (volatile struct espi_reg *const)DT_INST_REG_ADDR_BY_NAME(0, espi_target),
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.espislv_clk_grp = DT_CLOCKS_CELL_BY_NAME(DT_DRV_INST(0), espi_target, clk_grp),
16811783
.espislv_clk_idx = DT_CLOCKS_CELL_BY_NAME(DT_DRV_INST(0), espi_target, clk_idx),
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#ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
1785+
.promt0_reg = (volatile struct acpi_reg *const)DT_INST_REG_ADDR_BY_NAME(0, promt0),
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.promt0_clk_grp = DT_CLOCKS_CELL_BY_NAME(DT_DRV_INST(0), promt0, clk_grp),
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.promt0_clk_idx = DT_CLOCKS_CELL_BY_NAME(DT_DRV_INST(0), promt0, clk_idx),
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1789+
.emi0_reg = (volatile struct emi_reg *const)DT_INST_REG_ADDR_BY_NAME(0, emi0),
1790+
.emi0_clk_grp = DT_CLOCKS_CELL_BY_NAME(DT_DRV_INST(0), emi0, clk_grp),
1791+
.emi0_clk_idx = DT_CLOCKS_CELL_BY_NAME(DT_DRV_INST(0), emi0, clk_idx),
1792+
#endif
16821793
#ifdef CONFIG_ESPI_PERIPHERAL_DEBUG_PORT_80
16831794
.port80_reg = (volatile struct port80_reg *const)DT_INST_REG_ADDR_BY_NAME(0, port80),
16841795
.port80_clk_grp = DT_CLOCKS_CELL_BY_NAME(DT_DRV_INST(0), port80, clk_grp),

‎soc/realtek/ec/rts5912/reg/reg_acpi.h

Lines changed: 59 additions & 0 deletions
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@@ -0,0 +1,59 @@
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/*
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* Copyright (c) 2025 Realtek, SIBG-SD7
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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7+
#ifndef ZEPHYR_SOC_REALTEK_RTS5912_REG_ACPI_H
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#define ZEPHYR_SOC_REALTEK_RTS5912_REG_ACPI_H
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10+
struct acpi_reg {
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uint32_t STS;
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uint32_t IB;
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uint32_t OB;
14+
uint32_t PTADDR;
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uint32_t INTEN;
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uint32_t VWCTRL0;
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uint32_t VWCTRL1;
18+
};
19+
20+
/* STS */
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#define ACPI_STS_OBF BIT(0)
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#define ACPI_STS_IBF BIT(1)
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#define ACPI_STS_STS0 BIT(2)
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#define ACPI_STS_CMDSEL BIT(3)
25+
#define ACPI_STS_BURST BIT(4)
26+
#define ACPI_STS_STS2 BIT(5)
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#define ACPI_STS_STS3 BIT(6)
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#define ACPI_STS_STS4 BIT(7)
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/* IB */
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#define ACPI_IB_IBDAT_Pos (0UL)
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#define ACPI_IB_IBDAT_Msk GENMASK(7, 0)
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#define ACPI_IB_IBCLR BIT(8)
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/* OB */
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#define ACPI_OB_OBDAT_Pos (0UL)
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#define ACPI_OB_OBDAT_Msk GENMASK(7, 0)
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#define ACPI_OB_OBCLR BIT(8)
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/* PTADDR */
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#define ACPI_PTADDR_ADDR_Pos (0UL)
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#define ACPI_PTADDR_ADDR_Msk GENMASK(11, 0)
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#define ACPI_PTADDR_OFFSET_Pos (12UL)
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#define ACPI_PTADDR_OFFSET_Msk GENMASK(14, 12)
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/* INTEN */
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#define ACPI_INTEN_OBFINTEN BIT(0)
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#define ACPI_INTEN_IBFINTEN BIT(1)
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/* VWCTRL0 */
51+
#define ACPI_VWCTRL0_IRQEN BIT(0)
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#define ACPI_VWCTRL0_TGLV BIT(1)
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54+
/* VWCTRL1 */
55+
#define ACPI_VWCTRL1_IRQNUM_Pos (0UL)
56+
#define ACPI_VWCTRL1_IRQNUM_Msk GENMASK(7, 0)
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#define ACPI_VWCTRL1_ACTEN BIT(8)
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59+
#endif /* ZEPHYR_SOC_REALTEK_RTS5912_REG_ACPI_H */

‎soc/realtek/ec/rts5912/reg/reg_emi.h

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
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/*
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* Copyright (c) 2025 Realtek, SIBG-SD7
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_REALTEK_RTS5912_REG_EMI_H
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#define ZEPHYR_SOC_REALTEK_RTS5912_REG_EMI_H
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struct emi_reg {
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uint32_t CFG;
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uint32_t INTCTRL;
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uint32_t IRQNUM;
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uint32_t SAR;
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uint32_t INTSTS;
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uint32_t STS;
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};
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#endif /* ZEPHYR_SOC_REALTEK_RTS5912_REG_EMI_H */

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