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drivers/flash/nrf_qspi_nor: Default write_from_nvmc buffer size to 4
The commit changes the default size of write_from_nvmc, defined by CONFIG_NORDIC_QSPI_NOR_STACK_WRITE_BUFFER_SIZE, to 4, making the write_from_nvmc operation enabled by default. The Kconfig description for the option has been changes more clearly describe how does the option impact compilation. Signed-off-by: Dominik Ermel <[email protected]>
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+17
-19
lines changed

2 files changed

+17
-19
lines changed

drivers/flash/Kconfig.nordic_qspi_nor

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ config NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE
2828

2929
config NORDIC_QSPI_NOR_STACK_WRITE_BUFFER_SIZE
3030
int "Size of a stack-based buffer to support writes from NVMC"
31-
default 0
31+
default 4
3232
help
3333
The QSPI peripheral uses DMA and cannot write data that is
3434
read from the internal flash. A non-zero value here enables

drivers/flash/nrf_qspi_nor.c

Lines changed: 16 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -810,8 +810,6 @@ static inline nrfx_err_t write_sub_word(const struct device *dev, off_t addr,
810810
BUILD_ASSERT((CONFIG_NORDIC_QSPI_NOR_STACK_WRITE_BUFFER_SIZE % 4) == 0,
811811
"NOR stack buffer must be multiple of 4 bytes");
812812

813-
#define NVMC_WRITE_OK (CONFIG_NORDIC_QSPI_NOR_STACK_WRITE_BUFFER_SIZE > 0)
814-
815813
/* If enabled write using a stack-allocated aligned SRAM buffer as
816814
* required for DMA transfers by QSPI peripheral.
817815
*
@@ -820,28 +818,28 @@ BUILD_ASSERT((CONFIG_NORDIC_QSPI_NOR_STACK_WRITE_BUFFER_SIZE % 4) == 0,
820818
static inline nrfx_err_t write_from_nvmc(const struct device *dev, off_t addr,
821819
const void *sptr, size_t slen)
822820
{
823-
#if NVMC_WRITE_OK
824-
uint8_t __aligned(4) buf[CONFIG_NORDIC_QSPI_NOR_STACK_WRITE_BUFFER_SIZE];
825-
const uint8_t *sp = sptr;
826821
nrfx_err_t res = NRFX_SUCCESS;
827822

828-
while ((slen > 0) && (res == NRFX_SUCCESS)) {
829-
size_t len = MIN(slen, sizeof(buf));
823+
if (CONFIG_NORDIC_QSPI_NOR_STACK_WRITE_BUFFER_SIZE > 0) {
824+
uint8_t __aligned(4) buf[CONFIG_NORDIC_QSPI_NOR_STACK_WRITE_BUFFER_SIZE];
825+
const uint8_t *sp = sptr;
830826

831-
memcpy(buf, sp, len);
832-
res = nrfx_qspi_write(buf, sizeof(buf),
833-
addr);
834-
qspi_wait_for_completion(dev, res);
827+
while ((slen > 0) && (res == NRFX_SUCCESS)) {
828+
size_t len = MIN(slen, sizeof(buf));
835829

836-
if (res == NRFX_SUCCESS) {
837-
slen -= len;
838-
sp += len;
839-
addr += len;
830+
memcpy(buf, sp, len);
831+
res = nrfx_qspi_write(buf, sizeof(buf), addr);
832+
qspi_wait_for_completion(dev, res);
833+
834+
if (res == NRFX_SUCCESS) {
835+
slen -= len;
836+
sp += len;
837+
addr += len;
838+
}
840839
}
840+
} else {
841+
res = NRFX_ERROR_INVALID_ADDR;
841842
}
842-
#else /* NVMC_WRITE_OK */
843-
nrfx_err_t res = NRFX_ERROR_INVALID_ADDR;
844-
#endif /* NVMC_WRITE_OK */
845843
return res;
846844
}
847845

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