boards: intel: btl: Added revisions to support Hybrid and 12P

Added revisions to support Hybrid and 12P versions of
Bartlett Lake Platform.

Signed-off-by: Anisetti Avinash Krishna <[email protected]>

Author: akanisetti

boards/intel/btl/Kconfig.defconfig

@@ -10,6 +10,8 @@ config MP_MAX_NUM_CPUS
 
 # TSC on this board is 2.9 GHz, HPET is 19.2 MHz
 config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 3300000000 if APIC_TSC_DEADLINE_TIMER && BOARD_REVISION="P"
+	default 3300000000 if APIC_TIMER_TSC && BOARD_REVISION="P"
 	default 2900000000 if APIC_TSC_DEADLINE_TIMER
 	default 2900000000 if APIC_TIMER_TSC
 	default 19200000

boards/intel/btl/board.yml

@@ -2,5 +2,12 @@ boards:
   - name: intel_btl_s_crb
     full_name: Bartlett Lake P CRB
     vendor: intel
+    revision:
+      format: letter
+      default: "H"
+      exact: true
+      revisions:
+        - name: "H"
+        - name: "P"
     socs:
       - name: raptor_lake

boards/intel/btl/doc/index.rst

@@ -2,9 +2,15 @@
 
 Overview
 ********
-Bartlett Lake processor is a 64-bit multi-core processor built on Intel 7 process
-Technology. Bartlett Lake is based on a Hybrid architecture, utilizing
-P-cores for performance and E-Cores for efficiency.
+The Bartlett Lake processor is a 64-bit multi-core processor built on Intel's 7 process technology.
+
+It is available in two versions, one version is based on a hybrid architecture utilizing both
+P-cores for performance and E-cores for efficiency, while the other version is based solely on
+P-cores. These two versions are enabled as two revisions in Zephyr, as listed below:
+* Revision "H" - BTL-s Hybrid
+* Revision "P" - BTL-s 12P
+
+Default revision H is selected. To build for revision P, use ``intel_btl_s_crb@P``.
 
 The S-Processor line is a 2-Chip Platform that includes the Processor Die and
 Platform Controller Hub (PCH-S) Die in the Package.