dts: renesas: Add Watchdog support for RZ/A3UL, N2L, T2M

Add Watchdog nodes to Renesas RZ/A3UL, N2L, T2M devicetree

Signed-off-by: Quang Le <[email protected]>
Signed-off-by: Tien Nguyen <[email protected]>

Author: le-quang168

dts/arm/renesas/rz/rzn/r9a07g084.dtsi

@@ -4,6 +4,7 @@
  */
 
 #include <mem.h>
+#include <freq.h>
 #include <arm/armv8-r.dtsi>
 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
 #include <zephyr/dt-bindings/adc/adc.h>
@@ -1144,5 +1145,13 @@
 				status = "disabled";
 			};
 		};
+
+		wdt0: watchdog@80042000 {
+			compatible = "renesas,rz-wdt";
+			reg = <0x80042000 0x1000>;
+			clock-freq = <DT_FREQ_M(50)>;
+			interrupts = <GIC_SPI 388 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+			status = "disabled";
+		};
 	};
 };

dts/arm/renesas/rz/rzt/r9a07g075.dtsi

@@ -6,6 +6,7 @@
  */
 
 #include <mem.h>
+#include <freq.h>
 #include <arm/armv8-r.dtsi>
 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
 #include <zephyr/dt-bindings/adc/adc.h>
@@ -1143,5 +1144,13 @@
 				status = "disabled";
 			};
 		};
+
+		wdt0: watchdog@80042000 {
+			compatible = "renesas,rz-wdt";
+			reg = <0x80042000 0x1000>;
+			clock-freq = <DT_FREQ_M(50)>;
+			interrupts = <GIC_SPI 388 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+			status = "disabled";
+		};
 	};
 };

dts/arm64/renesas/rz/rza/r9a07g063.dtsi

@@ -688,5 +688,13 @@
 				status = "disabled";
 			};
 		};
+
+		wdt0: watchdog@12800800 {
+			compatible = "renesas,rz-wdt";
+			reg = <0x12800800 DT_SIZE_K(1)>;
+			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clock-freq = <DT_FREQ_M(24)>;
+			status = "disabled";
+		};
 	};
 };