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boards: sc: Add SC-OBC module V1 support
Add initial board support for the Space Cubics SC-OBC Module V1. The hardware is based on an AMD Versal AI Edge VE2302 and a Microchip IGLOO2. This Zephyr port runs on the Versal device’s Real-Time Processing Unit (dual Arm Cortex-R5F). This commit is the first in the series and only supports the basic devices needed to run samples/hello_world and samples/philosophers. Specifically, it adds the Cortex-R5F, UARTs, and the GIC interrupt controller. Signed-off-by: Yasushi SHOJI <[email protected]>
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‎boards/sc/scobc_v1/Kconfig.scobc_v1‎

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#
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# Copyright (c) 2025 Space Cubics Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config BOARD_SCOBC_V1
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select SOC_VERSAL_RPU

‎boards/sc/scobc_v1/board.cmake‎

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#
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# Copyright (c) 2025 Space Cubics Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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include(${ZEPHYR_BASE}/boards/common/xsdb.board.cmake)

‎boards/sc/scobc_v1/board.yml‎

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board:
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name: scobc_v1
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full_name: SC-OBC Module V1
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vendor: sc
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socs:
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- name: versal_rpu

‎boards/sc/scobc_v1/doc/index.rst‎

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.. zephyr:board:: scobc_v1
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Overview
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********
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The `Space Cubics`_ OBC Module V1 (SC-OBC Module V1) is an onboard computer
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for space missions that require reliable real-time control and edge
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processing. It is built around an AMD Versal Adaptive SoC and a Microchip
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IGLOO2 FPGA, and is designed for harsh environments such as Earth orbit and
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lunar missions.
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On the Versal side, the SC-OBC V1 leverages the device’s heterogeneous
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architecture, combining general-purpose processors, programmable logic, and a
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vector processor, to run on-orbit workloads such as object detection, image
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compression/segmentation, and high-speed signal processing, while keeping
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flight-critical tasks under Zephyr RTOS’s predictable scheduling model.
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On the IGLOO2 side, the SC-OBC V1 uses the device as the board’s safety
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processor, supervising the main system, providing independent watchdog and
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fault-management paths, and coordinating safe-mode transitions to improve fault
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tolerance.
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Hardware
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********
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Supported Features
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==================
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.. zephyr:board-supported-hw::
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System Clock
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============
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This board provides a 50 MHz reference oscillator for clock generation. The RPU
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(Cortex-R5F) runs at 600 MHz by default on this board.
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In Zephyr, the "system clock" is the kernel’s tick base. By default it’s 100 Hz
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for periodic-tick builds and 10 kHz (10000 Hz) for tickless builds. See
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:kconfig:option:`CONFIG_SYS_CLOCK_TICKS_PER_SEC` for more details.
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Serial Port
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===========
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The SC-OBC Module V1 has multiple UART ports. The primary ports are routed to
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the FT4232H on the evaluation board, so when you connect the board to your PC
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with a USB Type-C cable, your development machine will enumerate them.
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- Port A is used for JTAG.
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- Port B connects to UART0 via LPD MIO pin 0 (RXD) and pin 1 (TXD) on Bank 502.
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- Port C connects to UART1 via LPD MIO pin 4 (TXD) and pin 5 (RXD) on Bank 502.
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For Zephyr on Versal RPU, UART1 is selected as the default console in
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:file:`scobc_v1_versal_rpu.dts`. On a Linux host, the console typically
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appears as something like ``/dev/ttyUSB2`` (device index may vary).
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- Port D connects to IGLOO2.
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Programming and Debugging
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*************************
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.. zephyr:board-supported-runners::
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Flashing
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========
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Here is an example for building and flashing the :zephyr:code-sample:`hello_world` application
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for the board:
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: scobc_v1
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:goals: flash
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:flash-args: --pdi /path/to/your.pdi
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After flashing, you should see message similar to the following in the terminal:
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.. code-block:: console
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*** Booting Zephyr OS build v4.2.0 ***
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Hello World! scobc_v1/versal_rpu
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References
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**********
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.. target-notes::
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.. _Space Cubics:
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https://spacecubics.com/

‎boards/sc/scobc_v1/doc/scobc_v1.webp‎

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‎boards/sc/scobc_v1/scobc_v1_versal_rpu.dts‎

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/*
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* Copyright (c) 2025 Space Cubics Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <arm/xilinx/versal_rpu.dtsi>
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/ {
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model = "SC-OBC Module V1 Versal Cortex-R5F";
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chosen {
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zephyr,sram = &tcm;
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zephyr,console = &uart1;
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zephyr,shell-uart = &uart1;
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zephyr,ocm = &ocm;
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};
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};
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&uart1 {
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status = "okay";
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current-speed = <115200>;
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clock-frequency = <100000000>;
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};
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&uart0 {
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status = "okay";
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current-speed = <115200>;
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clock-frequency = <100000000>;
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};
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&ttc0 {
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status = "okay";
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clock-frequency = <150000000>;
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};

‎boards/sc/scobc_v1/scobc_v1_versal_rpu.yaml‎

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identifier: scobc_v1
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name: SC-OC Module V1 Versal AI Edge RPU
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arch: arm
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toolchain:
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- zephyr
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vendor: sc
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supported:
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- uart

‎boards/sc/scobc_v1/scobc_v1_versal_rpu_defconfig‎

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# Enable UART driver
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CONFIG_SERIAL=y
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# Enable console
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y

‎boards/sc/scobc_v1/support/xsdb.cfg‎

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# Copyright (c) 2025 Advanced Micro Devices, Inc.
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# Copyright (c) 2025 Space Cubics Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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proc program_pdi pdi_file {
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targets -set -filter {name =~ "Versal *"}
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after 300
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rst
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device program $pdi_file
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}
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proc rpu0_core0_rst {} {
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targets -set -filter {name =~ "Versal *"}
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after 300
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# Enable write to CRF by CRL.WPROT = 0
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mwr -force 0xff5e001c 0
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# Deassert CRL.POR, AMBA, RPU1, RPU0
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mwr -force 0xff5e0300 0
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}
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proc download_elf elf_file {
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targets -set -filter {name =~ "Cortex-R5 #0"}
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after 300
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stop
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after 1000
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dow -force $elf_file
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con
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}
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proc load_image args {
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if {[llength $args] != 2} {
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puts stderr "\nusage: west flash --pdi /path/to/your.pdi"
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puts stderr "For more details, do\n\twest flash --context -r xsdb\n"
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}
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set elf_file [lindex $args 0]
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set pdi_file [lindex $args 1]
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if { [info exists ::env(HW_SERVER_URL)] } {
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connect -url $::env(HW_SERVER_URL)
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} else {
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connect
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}
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program_pdi $pdi_file
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rpu0_core0_rst
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download_elf $elf_file
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exit
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}
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load_image {*}$argv

‎dts/arm/xilinx/versal_rpu.dtsi‎

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/*
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* Copyright (c) 2025 Space Cubics Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <freq.h>
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#include <arm/armv7-r.dtsi>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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#include <amd/versal.dtsi>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-r5f";
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reg = <0>;
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};
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};
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tcm: memory@0 {
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device_type = "memory";
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x00000000 DT_SIZE_K(128)>;
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zephyr,memory-region = "TCM";
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};
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soc {
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interrupt-parent = <&gic>;
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gic: interrupt-controller@f9000000 {
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compatible = "arm,gic-v1", "arm,gic";
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reg = <0xf9000000 0x1000>,
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<0xf9001000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <4>;
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status = "okay";
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};
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};
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};

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