boards: Add Space Cubics OBC Module 1

This is a single board computer for spacecraft OBC (On-board Computer).
It has a Xilinx FPGA with Cortex ARM M3 core with peripherals, UART, CAN
and others.

Signed-off-by: Yasushi SHOJI <[email protected]>

Author: yashi

CODEOWNERS

@@ -135,6 +135,7 @@
 /boards/arm/sam4s_xplained/               @fallrisk
 /boards/arm/sam_e70_xplained/             @nandojve
 /boards/arm/sam_v71_xult/                 @nandojve
+/boards/arm/scobc_module1/                @yashi
 /boards/arm/v2m_beetle/                   @fvincenzo
 /boards/arm/olimexino_stm32/              @ydamigos
 /boards/arm/sensortile_box/               @avisconti

boards/arm/scobc_module1/Kconfig.board

@@ -0,0 +1,8 @@
+# Space Cubics OBC module 1 configuration
+
+# Copyright (c) 2021 Space Cubics, LLC. <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_SCOBC_MODULE1
+	bool "Space Cubics OBC Module 1"
+	depends on SOC_SERIES_ARM_DESIGNSTART

boards/arm/scobc_module1/Kconfig.defconfig

@@ -0,0 +1,24 @@
+# Space Cubics OBC module 1
+
+# Copyright (c) 2021 Space Cubics <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_SCOBC_MODULE1
+
+config BOARD
+	default "scobc_module1"
+
+config CPU_CORTEX_M_HAS_SYSTICK
+	default y
+
+config CPU_HAS_ARM_MPU
+	default y
+
+config NUM_IRQS
+	default 7
+
+config UART_XLNX_UARTLITE
+	depends on SERIAL
+	default y
+
+endif # BOARD_SCOBC_SPEQ

boards/arm/scobc_module1/board.cmake

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_BOARD_SCOBC_MODULE1)
+  board_runner_args(openocd "--use-elf" "--config=${BOARD_DIR}/support/openocd-ftdi.cfg")
+
+  include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+endif()

boards/arm/scobc_module1/doc/index.rst

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+.. _scobc_module1:
+
+Space Cubics OBC module 1
+#########################
+
+Overview
+********
+
+`Space Cubics`_ OBC module 1 is a single board computer for spacecraft,
+especially for 3U CubeSats.  The board is based on Xilinx Artix-7 FPGA and
+implements ARM Cortex M3 as the main CPU.
+
+.. figure:: ./scobc.jpg
+   :width: 442px
+   :align: center
+   :alt: Space Cubics OBC module 1
+
+   Space Cubics OBC module 1
+
+It is designed to survive in the severe space environment, extreme temperature,
+vacuum, and space radiation.
+
+As the name suggests, the board form factor is a module and requires a base I/O
+board connected at CON1, a board-to-board connector.  This modularity allows
+CubeSat designers the freedom to connect and expand the capability required for
+their mission.
+
+Hardware
+********
+
+Supported Features
+==================
+
+The Space Cubics OBC module 1 provides the following hardware features:
+
++-----------+------------+------------------------------------+
+| Interface | Controller | Driver/Component                   |
++===========+============+====================================+
+| NVIC      | on-chip    | nested vector interrupt controller |
++-----------+------------+------------------------------------+
+| SYSTICK   | on-chip    | systick                            |
++-----------+------------+------------------------------------+
+| UART      | on-chip    | serial port-polling;               |
+|           |            | serial port-interrupt              |
++-----------+------------+------------------------------------+
+
+The default configuration for the board can be found in the defconfig file:
+:file:`boards/arm/scobc_module1/scobc_module1_defconfig`.
+
+Other hardware features are not currently supported by the port.
+
+System Clock
+============
+
+The board has two 24 MHz external oscillators connected to the FPGA for
+redundancy. The FPGA will select an active oscillator as CPU system clock.  The
+selected clock signal is then used by the CMT in the FPGA, and drives the CPU at
+48 MHz by default.
+
+Serial Port
+===========
+
+The default configuration contains one SC UART IP, which is register compatible
+with Xilinx UART Lite for basic TX and RX. This UART is configured as the
+default console and is accessible through the CON1 pin 43 and 45 for Rx and Tx,
+respectively.
+
+Programming and Debugging
+*************************
+
+Flashing
+========
+
+Here is an example for building and flashing the \`hello\_world\`
+application for the board:
+
+Here is an example for building and flashing the :ref:`hello_world` application
+for the default design:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: scobc_module1
+   :goals: flash
+
+After flashing, you should see message similar to the following in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build zephyr-v2.7.99  ***
+   Hello World! scobc_module1
+
+Note, however, that the application was not persisted in flash memory by the
+above steps. It was merely written to internal RAM in the FPGA.
+
+Debugging
+=========
+
+Here is an example for the :ref:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: scobc_module1
+   :goals: debug
+
+Step through the application in your debugger, and you should see a message
+similar to the following in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build zephyr-v2.7.99  ***
+   Hello World! scobc_module1
+
+References
+**********
+
+.. target-notes::
+
+.. _Space Cubics:
+   https://spacecubics.com/

boards/arm/scobc_module1/doc/scobc.jpg

@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: Apache-2.0
+
+description: Space Cubics HRMEM (High-reliability Memory)
+
+compatible: "sc,hrmem"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true

boards/arm/scobc_module1/dts/bindings/sc,hrmem.yaml

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2021 Space Cubics, LLC. <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <arm/armv7-m.dtsi>
+#include <mem.h>
+
+/ {
+	model = "Space Cubics OBC module 1";
+
+	chosen {
+		zephyr,console = &uartlite0;
+		zephyr,shell-uart = &uartlite0;
+		zephyr,sram = &hrmem;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m3";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv7m-mpu";
+				reg = <0xe000ed90 0x40>;
+				arm,num-mpu-regions = <8>;
+			};
+		};
+	};
+
+	soc {
+		hrmem: memory@0 {
+			compatible = "sc,hrmem";
+			reg = <0x00000000 DT_SIZE_K(128)>;
+		};
+
+		uartlite0: uartlite@50010000 {
+			compatible = "xlnx,xps-uartlite-1.00.a";
+			interrupts = <0 0>;
+			reg = <0x50010000 0x10000>;
+			label = "UART_0";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};

boards/arm/scobc_module1/scobc_module1.dts

@@ -0,0 +1,8 @@
+identifier: scobc_module1
+name: Space Cubics OBC module 1
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+supported:
+  - uart

boards/arm/scobc_module1/scobc_module1.yaml

@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_CORTEX_M_SYSTICK=y
+CONFIG_SOC_SERIES_ARM_DESIGNSTART=y
+CONFIG_SOC_ARM_DESIGNSTART_FPGA_CORTEX_M3=y
+CONFIG_BOARD_SCOBC_MODULE1=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
+CONFIG_ARM_MPU=n
+
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+CONFIG_XIP=n
+CONFIG_FLASH_SIZE=0
+CONFIG_FLASH_BASE_ADDRESS=0x0
+CONFIG_BOOTLOADER_SRAM_SIZE=0