@@ -50,6 +50,21 @@ void radio_isr_set(radio_isr_fp fp_radio_isr)
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void radio_setup (void )
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{
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+ #if defined(CONFIG_BT_CTLR_GPIO_PA_PIN )
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+ NRF_GPIO -> DIRSET = BIT (CONFIG_BT_CTLR_GPIO_PA_PIN );
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+ #if defined(CONFIG_BT_CTLR_GPIO_PA_POL_INV )
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+ NRF_GPIO -> OUTSET = BIT (CONFIG_BT_CTLR_GPIO_PA_PIN );
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+ #else
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+ NRF_GPIO -> OUTCLR = BIT (CONFIG_BT_CTLR_GPIO_PA_PIN );
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+ #endif
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+ #endif /* CONFIG_BT_CTLR_GPIO_PA_PIN */
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+
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+ #if defined(CONFIG_BT_CTLR_GPIO_LNA_PIN )
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+ NRF_GPIO -> DIRSET = BIT (CONFIG_BT_CTLR_GPIO_LNA_PIN );
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+
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+ radio_gpio_lna_off ();
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+ #endif /* CONFIG_BT_CTLR_GPIO_LNA_PIN */
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+
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#if defined(CONFIG_SOC_SERIES_NRF52X )
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struct {
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u32_t volatile reserved_0 [0x5a0 >> 2 ];
@@ -719,6 +734,38 @@ void radio_tmr_start_us(u8_t trx, u32_t us)
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NRF_PPI -> CHENSET = PPI_CHEN_CH0_Msk ;
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}
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+ u32_t radio_tmr_start_now (u8_t trx )
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+ {
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+ u32_t now , start ;
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+
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+ /* Setup PPI for Radio start */
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+ NRF_PPI -> CH [0 ].EEP = (u32_t )& (NRF_TIMER0 -> EVENTS_COMPARE [0 ]);
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+ NRF_PPI -> CH [0 ].TEP = (trx ) ? (u32_t )& (NRF_RADIO -> TASKS_TXEN ) :
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+ (u32_t )& (NRF_RADIO -> TASKS_RXEN );
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+ NRF_PPI -> CHENSET = PPI_CHEN_CH0_Msk ;
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+
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+ /* Capture the current time */
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+ NRF_TIMER0 -> TASKS_CAPTURE [1 ] = 1 ;
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+ now = NRF_TIMER0 -> CC [1 ];
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+ start = now ;
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+
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+ /* Setup PPI while determining the latency in doing so */
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+ do {
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+ /* Set start to be, now plus the determined latency */
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+ start = (now << 1 ) - start ;
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+
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+ /* Setup compare event with min. 1 us offset */
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+ NRF_TIMER0 -> CC [0 ] = start + 1 ;
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+ NRF_TIMER0 -> EVENTS_COMPARE [0 ] = 0 ;
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+
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+ /* Capture the current time */
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+ NRF_TIMER0 -> TASKS_CAPTURE [1 ] = 1 ;
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+ now = NRF_TIMER0 -> CC [1 ];
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+ } while (now > start );
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+
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+ return start ;
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+ }
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+
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void radio_tmr_stop (void )
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{
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NRF_TIMER0 -> TASKS_STOP = 1 ;
@@ -796,6 +843,88 @@ u32_t radio_tmr_sample_get(void)
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return NRF_TIMER0 -> CC [3 ];
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}
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+ #if defined(CONFIG_BT_CTLR_GPIO_PA_PIN ) || \
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+ defined(CONFIG_BT_CTLR_GPIO_LNA_PIN )
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+ #if defined(CONFIG_BT_CTLR_GPIO_PA_PIN )
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+ void radio_gpio_pa_setup (void )
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+ {
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+ NRF_GPIOTE -> CONFIG [CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN ] =
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+ (GPIOTE_CONFIG_MODE_Task <<
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+ GPIOTE_CONFIG_MODE_Pos ) |
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+ (CONFIG_BT_CTLR_GPIO_PA_PIN <<
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+ GPIOTE_CONFIG_PSEL_Pos ) |
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+ (GPIOTE_CONFIG_POLARITY_Toggle <<
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+ GPIOTE_CONFIG_POLARITY_Pos ) |
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+ #if defined(CONFIG_BT_CTLR_GPIO_PA_POL_INV )
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+ (GPIOTE_CONFIG_OUTINIT_High <<
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+ GPIOTE_CONFIG_OUTINIT_Pos );
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+ #else
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+ (GPIOTE_CONFIG_OUTINIT_Low <<
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+ GPIOTE_CONFIG_OUTINIT_Pos );
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+ #endif
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+ }
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+ #endif /* CONFIG_BT_CTLR_GPIO_PA_PIN */
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+
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+ #if defined(CONFIG_BT_CTLR_GPIO_LNA_PIN )
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+ void radio_gpio_lna_setup (void )
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+ {
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+ NRF_GPIOTE -> CONFIG [CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN ] =
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+ (GPIOTE_CONFIG_MODE_Task <<
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+ GPIOTE_CONFIG_MODE_Pos ) |
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+ (CONFIG_BT_CTLR_GPIO_LNA_PIN <<
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+ GPIOTE_CONFIG_PSEL_Pos ) |
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+ (GPIOTE_CONFIG_POLARITY_Toggle <<
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+ GPIOTE_CONFIG_POLARITY_Pos ) |
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+ #if defined(CONFIG_BT_CTLR_GPIO_LNA_POL_INV )
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+ (GPIOTE_CONFIG_OUTINIT_High <<
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+ GPIOTE_CONFIG_OUTINIT_Pos );
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+ #else
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+ (GPIOTE_CONFIG_OUTINIT_Low <<
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+ GPIOTE_CONFIG_OUTINIT_Pos );
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+ #endif
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+ }
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+
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+ void radio_gpio_lna_on (void )
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+ {
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+ #if defined(CONFIG_BT_CTLR_GPIO_LNA_POL_INV )
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+ NRF_GPIO -> OUTCLR = BIT (CONFIG_BT_CTLR_GPIO_LNA_PIN );
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+ #else
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+ NRF_GPIO -> OUTSET = BIT (CONFIG_BT_CTLR_GPIO_LNA_PIN );
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+ #endif
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+ }
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+
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+ void radio_gpio_lna_off (void )
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+ {
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+ #if defined(CONFIG_BT_CTLR_GPIO_LNA_POL_INV )
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+ NRF_GPIO -> OUTSET = BIT (CONFIG_BT_CTLR_GPIO_LNA_PIN );
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+ #else
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+ NRF_GPIO -> OUTCLR = BIT (CONFIG_BT_CTLR_GPIO_LNA_PIN );
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+ #endif
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+ }
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+ #endif /* CONFIG_BT_CTLR_GPIO_LNA_PIN */
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+
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+ void radio_gpio_pa_lna_enable (u32_t trx_us )
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+ {
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+ NRF_TIMER0 -> CC [2 ] = trx_us ;
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+ NRF_TIMER0 -> EVENTS_COMPARE [2 ] = 0 ;
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+
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+ NRF_PPI -> CH [7 ].EEP = (u32_t )& (NRF_TIMER0 -> EVENTS_COMPARE [2 ]);
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+ NRF_PPI -> CH [7 ].TEP = (u32_t )
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+ & (NRF_GPIOTE -> TASKS_OUT [CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN ]);
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+
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+ NRF_PPI -> CH [8 ].EEP = (u32_t )& (NRF_RADIO -> EVENTS_DISABLED );
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+ NRF_PPI -> CH [8 ].TEP = (u32_t )
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+ & (NRF_GPIOTE -> TASKS_OUT [CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN ]);
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+
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+ NRF_PPI -> CHENSET = PPI_CHEN_CH7_Msk | PPI_CHEN_CH8_Msk ;
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+ }
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+
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+ void radio_gpio_pa_lna_disable (void )
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+ {
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+ NRF_PPI -> CHENCLR = PPI_CHEN_CH7_Msk | PPI_CHEN_CH8_Msk ;
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+ }
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+ #endif /* CONFIG_BT_CTLR_GPIO_PA_PIN || CONFIG_BT_CTLR_GPIO_LNA_PIN */
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+
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static u8_t MALIGN (4 ) _ccm_scratch [(RADIO_PDU_LEN_MAX - 4 ) + 16 ];
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void * radio_ccm_rx_pkt_set (struct ccm * ccm , void * pkt )
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