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boards: frdm_mcxa344: add frdm_mcxa344 board
enable board support for frdm_mcxa344 Signed-off-by: Neil Chen <[email protected]>
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‎boards/nxp/frdm_mcxa344/CMakeLists.txt‎

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#
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# Copyright 2025 NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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zephyr_library()
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zephyr_library_sources(board.c)

‎boards/nxp/frdm_mcxa344/Kconfig‎

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# Copyright 2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_FRDM_MCXA344
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select BOARD_EARLY_INIT_HOOK

‎boards/nxp/frdm_mcxa344/Kconfig.frdm_mcxa344‎

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# Copyright 2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_FRDM_MCXA344
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select SOC_MCXA344
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select SOC_PART_NUMBER_MCXA344VLL

‎boards/nxp/frdm_mcxa344/board.c‎

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/*
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* Copyright 2025 NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/init.h>
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#include <zephyr/device.h>
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#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
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#include <fsl_clock.h>
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#include <fsl_spc.h>
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#include <soc.h>
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/* Core clock frequency: 180MHz */
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#define CLOCK_INIT_CORE_CLOCK 180000000U
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#define BOARD_BOOTCLOCKFROHF180M_CORE_CLOCK 180000000U
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/* System clock frequency. */
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extern uint32_t SystemCoreClock;
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void board_early_init_hook(void)
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{
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uint32_t coreFreq;
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spc_active_mode_core_ldo_option_t ldoOption;
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spc_sram_voltage_config_t sramOption;
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/* Get the CPU Core frequency */
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coreFreq = CLOCK_GetCoreSysClkFreq();
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/* The flow of increasing voltage and frequency */
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if (coreFreq <= BOARD_BOOTCLOCKFROHF180M_CORE_CLOCK) {
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/* Set the LDO_CORE VDD regulator level */
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ldoOption.CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage;
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ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
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(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
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/* Configure Flash to support different voltage level and frequency */
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FMU0->FCTRL =
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(FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x4U));
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/* Specifies the operating voltage for the SRAM's read/write timing margin */
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sramOption.operateVoltage = kSPC_sramOperateAt1P2V;
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sramOption.requestVoltageUpdate = true;
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(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
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}
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/*!< Set up system dividers */
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CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set SYSCON.AHBCLKDIV divider to value 1 */
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CLOCK_SetClockDiv(kCLOCK_DivFRO_HF, 1U); /* !< Set SYSCON.FROHFDIV divider to value 1 */
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CLOCK_SetupFROHFClocking(BOARD_BOOTCLOCKFROHF180M_CORE_CLOCK); /*!< Enable FRO HF */
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CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
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CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to kFRO_HF */
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/* The flow of decreasing voltage and frequency */
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if (coreFreq > BOARD_BOOTCLOCKFROHF180M_CORE_CLOCK) {
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/* Configure Flash to support different voltage level and frequency */
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FMU0->FCTRL =
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(FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x4U));
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/* Specifies the operating voltage for the SRAM's read/write timing margin */
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sramOption.operateVoltage = kSPC_sramOperateAt1P2V;
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sramOption.requestVoltageUpdate = true;
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(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
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/* Set the LDO_CORE VDD regulator level */
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ldoOption.CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage;
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ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
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(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
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}
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */
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/*!< Set up dividers */
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CLOCK_SetClockDiv(kCLOCK_DivFRO_LF, 1U); /* !< Set SYSCON.FROLFDIV divider to value 1 */
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CLOCK_SetClockDiv(kCLOCK_DivTRACE, 2U); /* !< Set MRCC.TRACE_CLKDIV divider to value 2 */
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(porta))
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RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
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CLOCK_EnableClock(kCLOCK_GatePORT0);
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portb))
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RESET_ReleasePeripheralReset(kPORT1_RST_SHIFT_RSTn);
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CLOCK_EnableClock(kCLOCK_GatePORT1);
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portc))
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RESET_ReleasePeripheralReset(kPORT2_RST_SHIFT_RSTn);
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CLOCK_EnableClock(kCLOCK_GatePORT2);
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portd))
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RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
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CLOCK_EnableClock(kCLOCK_GatePORT3);
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(porte))
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RESET_ReleasePeripheralReset(kPORT4_RST_SHIFT_RSTn);
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CLOCK_EnableClock(kCLOCK_GatePORT4);
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio0))
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RESET_ReleasePeripheralReset(kGPIO0_RST_SHIFT_RSTn);
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CLOCK_EnableClock(kCLOCK_GateGPIO0);
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1))
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RESET_ReleasePeripheralReset(kGPIO1_RST_SHIFT_RSTn);
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CLOCK_EnableClock(kCLOCK_GateGPIO1);
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio2))
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RESET_ReleasePeripheralReset(kGPIO2_RST_SHIFT_RSTn);
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CLOCK_EnableClock(kCLOCK_GateGPIO2);
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio3))
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RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn);
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CLOCK_EnableClock(kCLOCK_GateGPIO3);
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio4))
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RESET_ReleasePeripheralReset(kGPIO4_RST_SHIFT_RSTn);
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CLOCK_EnableClock(kCLOCK_GateGPIO4);
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart0))
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CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
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CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART0);
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RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart1))
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CLOCK_SetClockDiv(kCLOCK_DivLPUART1, 1u);
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CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART1);
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RESET_ReleasePeripheralReset(kLPUART1_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart2))
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CLOCK_SetClockDiv(kCLOCK_DivLPUART2, 1u);
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CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART2);
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RESET_ReleasePeripheralReset(kLPUART2_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart3))
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CLOCK_SetClockDiv(kCLOCK_DivLPUART3, 1u);
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CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART3);
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RESET_ReleasePeripheralReset(kLPUART3_RST_SHIFT_RSTn);
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#endif
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/* Set SystemCoreClock variable. */
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SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
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}

‎boards/nxp/frdm_mcxa344/board.cmake‎

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#
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# Copyright 2025 NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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board_runner_args(jlink "--device=MCXA344")
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board_runner_args(linkserver "--device=MCXA344:FRDM-MCXA344")
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board_runner_args(pyocd "--target=MCXA344")
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include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)

‎boards/nxp/frdm_mcxa344/board.yml‎

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board:
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name: frdm_mcxa344
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full_name: FRDM-MCXA344
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vendor: nxp
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socs:
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- name: mcxa344

‎boards/nxp/frdm_mcxa344/doc/frdm_mcxa344.webp‎

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‎boards/nxp/frdm_mcxa344/doc/index.rst‎

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.. zephyr:board:: frdm_mcxa344
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Overview
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********
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FRDM-MCXA344 is a compact and scalable development board for rapid prototyping of MCX A344
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MCUs. They offer industry standard headers for easy access to the MCUs input/output (I/O),
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integrated open-standard serial interfaces, external flash memory and an onboard MCU-Link
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debugger.
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Hardware
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********
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- MCX-A344 Arm Cortex-M33 microcontroller running at 180 MHz
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- 256KB dual-bank on chip Flash
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- 64 KB RAM
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- 1x FlexCAN with FD, 1x RGB LED, 3x SW buttons
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- On-board MCU-Link debugger with CMSIS-DAP
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- Arduino Header, SmartDMA/Camera Header, mikroBUS
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For more information about the MCX-A344 SoC and FRDM-MCXA344 board, see:
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- `MCX-A344 SoC Website`_
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- `MCX-A344 Datasheet`_
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- `MCX-A344 Reference Manual`_
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- `FRDM-MCXA344 Website`_
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- `FRDM-MCXA344 User Guide`_
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- `FRDM-MCXA344 Board User Manual`_
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- `FRDM-MCXA344 Schematics`_
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Supported Features
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==================
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.. zephyr:board-supported-hw::
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Connections and IOs
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===================
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The MCX-A344 SoC has 5 gpio controllers and has pinmux registers which
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can be used to configure the functionality of a pin.
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+------------+-----------------+----------------------------+
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| Name | Function | Usage |
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+============+=================+============================+
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| PIO2_3 | UART | UART RX |
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+------------+-----------------+----------------------------+
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| PIO2_2 | UART | UART TX |
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+------------+-----------------+----------------------------+
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System Clock
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============
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The MCX-A344 SoC is configured to use FRO running at 180MHz as a source for
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the system clock.
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Serial Port
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===========
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The FRDM-MCXA344 SoC has 4 LPUART interfaces for serial communication.
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LPUART 2 is configured as UART for the console.
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Programming and Debugging
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*************************
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.. zephyr:board-supported-runners::
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Build and flash applications as usual (see :ref:`build_an_application` and
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:ref:`application_run` for more details).
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Configuring a Debug Probe
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=========================
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A debug probe is used for both flashing and debugging the board. This board is
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configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.
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Using LinkServer
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----------------
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Linkserver is the default runner for this board, and supports the factory
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default MCU-Link firmware. Follow the instructions in
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:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link
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firmware. This only needs to be done if the default onboard debug circuit
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firmware was changed. To put the board in ``ISP mode`` to program the firmware,
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short jumper JP4.
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Using J-Link
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------------
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There are two options. The onboard debug circuit can be updated with Segger
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J-Link firmware by following the instructions in
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:ref:`mcu-link-jlink-onboard-debug-probe`.
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To be able to program the firmware, you need to put the board in ``ISP mode``
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by shortening the jumper JP4.
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The second option is to attach a :ref:`jlink-external-debug-probe` to the
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10-pin SWD connector (J11) of the board. Additionally, the jumper JP6 must
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be shorted.
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For both options use the ``-r jlink`` option with west to use the jlink runner.
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.. code-block:: console
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west flash -r jlink
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Configuring a Console
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=====================
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Connect a USB cable from your PC to J13, and use the serial terminal of your choice
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(minicom, putty, etc.) with the following settings:
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- Speed: 115200
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- Data: 8 bits
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- Parity: None
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- Stop bits: 1
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Flashing
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========
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Here is an example for the :zephyr:code-sample:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: frdm_mcxa344
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:goals: flash
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Open a serial terminal, reset the board (press the RESET button), and you should
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see the following message in the terminal:
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.. code-block:: console
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*** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
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Hello World! frdm_mcxa344/mcxa344
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Debugging
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=========
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Here is an example for the :zephyr:code-sample:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: frdm_mcxa344/mcxa344
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:goals: debug
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Open a serial terminal, step through the application in your debugger, and you
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should see the following message in the terminal:
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.. code-block:: console
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*** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
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Hello World! frdm_mcxa344/mcxa344
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Troubleshooting
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===============
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.. include:: ../../common/segger-ecc-systemview.rst.inc
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.. include:: ../../common/board-footer.rst.inc
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.. _MCX-A344 SoC Website:
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https://www.nxp.com/products/MCX-A34X
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.. _MCX-A344 Datasheet:
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TBD
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.. _MCX-A344 Reference Manual:
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TBD
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.. _FRDM-MCXA344 Website:
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https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXA344
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.. _FRDM-MCXA344 User Guide:
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https://www.nxp.com/document/guide/getting-started-with-frdm-mcxa344:GS-FRDM-MCXA344
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.. _FRDM-MCXA344 Board User Manual:
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TBD
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.. _FRDM-MCXA344 Schematics:
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TBD

‎boards/nxp/frdm_mcxa344/frdm_mcxa344-pinctrl.dtsi‎

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/*
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* Copyright 2025 NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <nxp/mcx/MCXA344VLL-pinctrl.h>
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&pinctrl {
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pinmux_lpuart2: pinmux_lpuart2 {
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group0 {
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pinmux = <LPUART2_RXD_P2_3>,
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<LPUART2_TXD_P2_2>;
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drive-strength = "low";
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slew-rate = "fast";
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input-enable;
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};
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};
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};

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