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drivers: timer: riscv_machine_timer: Add support for T-Head C906
This commit adapts the existing RISC-V Machine Timer driver to support the
T-Head C906 core, which lacks a standard memory-mapped `MTIME` register.
Changes include:
* Added `mtime-is-32bits` and `mtimecmp-is-32bits` properties to support
SoCs where `MTIME`/`MTIMECMP` must be accessed as two separate 32-bit
registers, even on 64-bit platforms.
* Added `mtime-is-csr` property to allow reading the timer value from the
`time` CSR instead of a memory-mapped `MTIME` register.
* Made the `MTIME` register address optional in DTS; register addresses are
now resolved by `reg-names` instead of relying on index position.
Signed-off-by: Chen Xingyu <[email protected]>
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