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drivers: timer: riscv_machine_timer: Add support for T-Head C906
This commit adapts the existing RISC-V Machine Timer driver to support the T-Head C906 core, which lacks a standard memory-mapped `MTIME` register. Changes include: * Added `mtime-is-32bits` and `mtimecmp-is-32bits` properties to support SoCs where `MTIME`/`MTIMECMP` must be accessed as two separate 32-bit registers, even on 64-bit platforms. * Added `mtime-is-csr` property to allow reading the timer value from the `time` CSR instead of a memory-mapped `MTIME` register. * Made the `MTIME` register address optional in DTS; register addresses are now resolved by `reg-names` instead of relying on index position. Signed-off-by: Chen Xingyu <[email protected]>
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drivers/timer/riscv_machine_timer.c

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -16,9 +16,12 @@
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#define DT_DRV_COMPAT riscv_machine_timer
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#define MTIME_REG DT_INST_REG_ADDR_BY_NAME(0, mtime)
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#define MTIMECMP_REG DT_INST_REG_ADDR_BY_NAME(0, mtimecmp)
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#define TIMER_IRQN DT_INST_IRQN(0)
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#define MTIME_REG DT_INST_REG_ADDR_BY_NAME(0, mtime)
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#define MTIME_IS_CSR DT_INST_PROP(0, mtime_is_csr)
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#define MTIME_IS_32BITS DT_INST_PROP(0, mtime_is_32bits)
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#define MTIMECMP_REG DT_INST_REG_ADDR_BY_NAME(0, mtimecmp)
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#define MTIMECMP_IS_32BITS DT_INST_PROP(0, mtimecmp_is_32bits)
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#define TIMER_IRQN DT_INST_IRQN(0)
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#define CYC_PER_TICK (uint32_t)(sys_clock_hw_cycles_per_sec() / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
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@@ -67,7 +70,7 @@ static uintptr_t get_hart_mtimecmp(void)
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static void set_mtimecmp(uint64_t time)
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{
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#ifdef CONFIG_64BIT
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#if defined(CONFIG_64BIT) && !defined(MTIMECMP_IS_32BITS)
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*(volatile uint64_t *)get_hart_mtimecmp() = time;
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#else
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volatile uint32_t *r = (uint32_t *)get_hart_mtimecmp();
@@ -86,7 +89,9 @@ static void set_mtimecmp(uint64_t time)
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static uint64_t mtime(void)
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{
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#ifdef CONFIG_64BIT
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#if defined(MTIME_IS_CSR)
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return csr_read(time);
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#elif defined(CONFIG_64BIT) && !defined(MTIME_IS_32BITS)
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return *(volatile uint64_t *)MTIME_REG;
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#else
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volatile uint32_t *r = (uint32_t *)MTIME_REG;

dts/bindings/timer/riscv,machine-timer.yaml

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,3 +14,18 @@ properties:
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required: true
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interrupts-extended:
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required: true
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mtime-is-csr:
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type: boolean
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description: |
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If present, the value of the timer is read with the `time` CSR instead of
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the memory-mapped `MTIME` register.
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mtime-is-32bits:
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type: boolean
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description: |
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If present, the `MTIME` register is accessed as two separate 32-bit
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registers (low and high), even on 64-bit platforms.
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mtimecmp-is-32bits:
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type: boolean
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description: |
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If present, the `MTIMECMP` register is accessed as two separate 32-bit
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registers (low and high), even on 64-bit platforms.

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