|
| 1 | +.. zephyr:board:: nucleo_wba65ri |
| 2 | +
|
| 3 | +Overview |
| 4 | +******** |
| 5 | + |
| 6 | +NUCLEO-WBA65RI is a Bluetooth® Low Energy, 802.15.4 and Zigbee® wireless |
| 7 | +and ultra-low-power board embedding a powerful and ultra-low-power radio |
| 8 | +compliant with the Bluetooth® Low Energy SIG specification v5.4 |
| 9 | +with IEEE 802.15.4-2015 and Zigbee® specifications. |
| 10 | + |
| 11 | +The ARDUINO® Uno V3 connectivity support and the ST morpho headers allow the |
| 12 | +easy expansion of the functionality of the STM32 Nucleo open development |
| 13 | +platform with a wide choice of specialized shields. |
| 14 | + |
| 15 | +- Ultra-low-power wireless STM32WBA65RI microcontroller based on the Arm® |
| 16 | + Cortex®‑M33 core, featuring 2 Mbyte of flash memory and 512 Kbytes of SRAM in |
| 17 | + a VFQFPN68 package |
| 18 | + |
| 19 | +- MCU RF board (MB2130): |
| 20 | + |
| 21 | + - 2.4 GHz RF transceiver supporting Bluetooth® specification v5.4 |
| 22 | + - Arm® Cortex® M33 CPU with TrustZone®, MPU, DSP, and FPU |
| 23 | + - Integrated PCB antenna |
| 24 | + |
| 25 | +- Three user LEDs |
| 26 | +- Three user and one reset push-buttons |
| 27 | + |
| 28 | +- Board connectors: |
| 29 | + |
| 30 | + - 2 USB Type-C |
| 31 | + - ARDUINO® Uno V3 expansion connector |
| 32 | + - ST morpho headers for full access to all STM32 I/Os |
| 33 | + |
| 34 | +- Flexible power-supply options: ST-LINK USB VBUS or external sources |
| 35 | +- On-board STLINK-V3MODS debugger/programmer with USB re-enumeration capability: |
| 36 | + mass storage, Virtual COM port, and debug port |
| 37 | + |
| 38 | +Hardware |
| 39 | +******** |
| 40 | + |
| 41 | +The STM32WBA65xx multiprotocol wireless and ultralow power devices embed a |
| 42 | +powerful and ultralow power radio compliant with the Bluetooth® SIG Low Energy |
| 43 | +specification 5.4. They contain a high-performance Arm Cortex-M33 32-bit RISC |
| 44 | +core. They operate at a frequency of up to 100 MHz. |
| 45 | + |
| 46 | +- Includes ST state-of-the-art patented technology |
| 47 | + |
| 48 | +- Ultra low power radio: |
| 49 | + |
| 50 | + - 2.4 GHz radio |
| 51 | + - RF transceiver supporting Bluetooth® Low Energy 5.4 specification |
| 52 | + IEEE 802.15.4-2015 PHY and MAC, supporting Thread, Matter and Zigbee® |
| 53 | + - Proprietary protocols |
| 54 | + - RX sensitivity: -96 dBm (Bluetooth® Low Energy at 1 Mbps) |
| 55 | + and -100 dBm (IEEE 802.15.4 at 250 kbps) |
| 56 | + - Programmable output power, up to +10 dBm with 1 dB steps |
| 57 | + - Support for external PA |
| 58 | + - Integrated balun to reduce BOM |
| 59 | + - Suitable for systems requiring compliance with radio frequency regulations |
| 60 | + ETSI EN 300 328, EN 300 440, FCC CFR47 Part 15 and ARIB STD-T66 |
| 61 | + |
| 62 | +- Ultra low power platform with FlexPowerControl: |
| 63 | + |
| 64 | + - 1.71 to 3.6 V power supply |
| 65 | + - - 40 °C to 85 °C temperature range |
| 66 | + - Autonomous peripherals with DMA, functional down to Stop 1 mode |
| 67 | + - TBD nA Standby mode (16 wake-up pins) |
| 68 | + - TBD nA Standby mode with RTC |
| 69 | + - TBD µA Standby mode with 64 KB SRAM |
| 70 | + - TBD µA Stop 2 mode with 64 KB SRAM |
| 71 | + - TBD µA/MHz Run mode at 3.3 V |
| 72 | + - Radio: Rx TBD mA / Tx at 0 dBm TBD mA |
| 73 | + |
| 74 | +- Core: Arm® 32-bit Cortex®-M33 CPU with TrustZone®, MPU, DSP, and FPU |
| 75 | +- ART Accelerator™: 8-Kbyte instruction cache allowing 0-wait-state execution |
| 76 | + from flash memory (frequency up to 100 MHz, 150 DMIPS) |
| 77 | +- Power management: embedded regulator LDO and SMPS step-down converter |
| 78 | +- Supporting switch on-the-fly and voltage scaling |
| 79 | + |
| 80 | +- Benchmarks: |
| 81 | + |
| 82 | + - 1.5 DMIPS/MHz (Drystone 2.1) |
| 83 | + - 410 CoreMark® (4.10 CoreMark/MHz) |
| 84 | + |
| 85 | +- Clock sources: |
| 86 | + |
| 87 | + - 32 MHz crystal oscillator |
| 88 | + - 32 kHz crystal oscillator (LSE) |
| 89 | + - Internal low-power 32 kHz (±5%) RC |
| 90 | + - Internal 16 MHz factory trimmed RC (±1%) |
| 91 | + - PLL for system clock and ADC |
| 92 | + |
| 93 | +- Memories: |
| 94 | + |
| 95 | + - 2 MB flash memory with ECC, including 256 Kbytes with 100 cycles |
| 96 | + - 512 KB SRAM, including 64 KB with parity check |
| 97 | + - 512-byte (32 rows) OTP |
| 98 | + |
| 99 | +- Rich analog peripherals (independent supply): |
| 100 | + |
| 101 | + - 12-bit ADC 2.5 Msps with hardware oversampling |
| 102 | + |
| 103 | +- Communication peripherals: |
| 104 | + |
| 105 | + - Four UARTs (ISO 7816, IrDA, modem) |
| 106 | + - Three SPIs |
| 107 | + - Four I2C Fm+ (1 Mbit/s), SMBus/PMBus® |
| 108 | + |
| 109 | +- System peripherals: |
| 110 | + |
| 111 | + - Touch sensing controller, up to 24 sensors, supporting touch key, linear, |
| 112 | + rotary touch sensors |
| 113 | + - One 16-bit, advanced motor control timer |
| 114 | + - Three 16-bit timers |
| 115 | + - Two 32-bit timer |
| 116 | + - Two low-power 16-bit timers (available in Stop mode) |
| 117 | + - Two Systick timers |
| 118 | + - RTC with hardware calendar and calibration |
| 119 | + - Two watchdogs |
| 120 | + - 8-channel DMA controller, functional in Stop mode |
| 121 | + |
| 122 | +- Security and cryptography: |
| 123 | + |
| 124 | + - Arm® TrustZone® and securable I/Os, memories, and peripherals |
| 125 | + - Flexible life cycle scheme with RDP and password protected debug |
| 126 | + - Root of trust thanks to unique boot entry and secure hide protection area (HDP) |
| 127 | + - SFI (secure firmware installation) thanks to embedded RSS (root secure services) |
| 128 | + - Secure data storage with root hardware unique key (RHUK) |
| 129 | + - Secure firmware upgrade support with TF-M |
| 130 | + - Two AES co-processors, including one with DPA resistance |
| 131 | + - Public key accelerator, DPA resistant |
| 132 | + - HASH hardware accelerator |
| 133 | + - True random number generator, NIST SP800-90B compliant |
| 134 | + - 96-bit unique ID |
| 135 | + - Active tampers |
| 136 | + - CRC calculation unit |
| 137 | + |
| 138 | +- Up to 86 I/Os (most of them 5 V-tolerant) with interrupt capability |
| 139 | + |
| 140 | +- Development support: |
| 141 | + |
| 142 | + - Serial wire debug (SWD), JTAG |
| 143 | + |
| 144 | +- ECOPACK2 compliant package |
| 145 | + |
| 146 | +More information about STM32WBA series can be found here: |
| 147 | + |
| 148 | +- `STM32WBA Series on www.st.com`_ |
| 149 | + |
| 150 | +Supported Features |
| 151 | +================== |
| 152 | + |
| 153 | +.. zephyr:board-supported-hw:: |
| 154 | +
|
| 155 | +Connections and IOs |
| 156 | +=================== |
| 157 | + |
| 158 | +Nucleo WBA65RI Board has 4 GPIO controllers. These controllers are responsible for pin muxing, |
| 159 | +input/output, pull-up, etc. |
| 160 | + |
| 161 | +Default Zephyr Peripheral Mapping: |
| 162 | +---------------------------------- |
| 163 | + |
| 164 | +.. rst-class:: rst-columns |
| 165 | + |
| 166 | +- USART_1 TX/RX : PB12/PA8 |
| 167 | +- I2C_1_SCL : PB2 |
| 168 | +- I2C_1_SDA : PB1 |
| 169 | +- USER_PB : PC13 |
| 170 | +- LD1 : PD8 |
| 171 | +- SPI_1_NSS : PA12 (arduino_spi) |
| 172 | +- SPI_1_SCK : PB4 (arduino_spi) |
| 173 | +- SPI_1_MISO : PB3 (arduino_spi) |
| 174 | +- SPI_1_MOSI : PA15 (arduino_spi) |
| 175 | + |
| 176 | +System Clock |
| 177 | +------------ |
| 178 | + |
| 179 | +Nucleo WBA65RI System Clock could be driven by internal or external oscillator, |
| 180 | +as well as main PLL clock. By default System clock is driven by HSE+PLL clock at 100MHz. |
| 181 | + |
| 182 | +Serial Port |
| 183 | +----------- |
| 184 | + |
| 185 | +Nucleo WBA65RI board has 3 U(S)ARTs. The Zephyr console output is assigned to USART1. |
| 186 | +Default settings are 115200 8N1. |
| 187 | + |
| 188 | + |
| 189 | +Programming and Debugging |
| 190 | +************************* |
| 191 | + |
| 192 | +.. zephyr:board-supported-runners:: |
| 193 | +
|
| 194 | +Nucleo WBA65RI board includes an ST-LINK/V3 embedded debug tool interface. |
| 195 | +It could be used for flash and debug using either OpenOCD or STM32Cube ecosystem tools. |
| 196 | + |
| 197 | +Flashing |
| 198 | +======== |
| 199 | + |
| 200 | +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, |
| 201 | +so its :ref:`installation <stm32cubeprog-flash-host-tools>` is required. |
| 202 | + |
| 203 | +Alternatively, openocd can also be used to flash the board using |
| 204 | +the ``--runner`` (or ``-r``) option: |
| 205 | + |
| 206 | +.. code-block:: console |
| 207 | +
|
| 208 | + $ west flash --runner openocd |
| 209 | +
|
| 210 | +Flashing an application to Nucleo WBA65RI |
| 211 | +----------------------------------------- |
| 212 | + |
| 213 | +Here is an example for the :zephyr:code-sample:`blinky` application. |
| 214 | + |
| 215 | +.. zephyr-app-commands:: |
| 216 | + :zephyr-app: samples/basic/blinky |
| 217 | + :board: nucleo_wba65ri |
| 218 | + :goals: build flash |
| 219 | + |
| 220 | +You will see the LED blinking every second. |
| 221 | + |
| 222 | +Debugging |
| 223 | +========= |
| 224 | + |
| 225 | +Debugging using OpenOCD |
| 226 | +----------------------- |
| 227 | + |
| 228 | +You can debug an application in the usual way using OpenOCD. Here is an example for the |
| 229 | +:zephyr:code-sample:`blinky` application. |
| 230 | + |
| 231 | +.. zephyr-app-commands:: |
| 232 | + :zephyr-app: samples/basic/blinky |
| 233 | + :board: nucleo_wba65ri |
| 234 | + :maybe-skip-config: |
| 235 | + :goals: debug |
| 236 | + |
| 237 | +.. _STM32WBA Series on www.st.com: |
| 238 | + https://www.st.com/en/microcontrollers-microprocessors/stm32wba-series.html |
| 239 | + |
| 240 | +.. _STM32CubeProgrammer: |
| 241 | + https://www.st.com/en/development-tools/stm32cubeprog.html |
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