2525#include <zephyr/arch/xtensa/cache.h>
2626#endif
2727
28- #if defined(CONFIG_DCACHE )
28+ #if defined(CONFIG_DCACHE ) || defined( __DOXYGEN__ )
2929
3030/**
3131 * @brief Enable the d-cache
@@ -157,7 +157,7 @@ int arch_dcache_flush_and_invd_range(void *addr, size_t size);
157157#define cache_data_flush_and_invd_range (addr , size ) \
158158 arch_dcache_flush_and_invd_range(addr, size)
159159
160- #if defined(CONFIG_DCACHE_LINE_SIZE_DETECT )
160+ #if defined(CONFIG_DCACHE_LINE_SIZE_DETECT ) || defined( __DOXYGEN__ )
161161
162162/**
163163 *
@@ -176,11 +176,11 @@ size_t arch_dcache_line_size_get(void);
176176
177177#define cache_data_line_size_get arch_dcache_line_size_get
178178
179- #endif /* CONFIG_DCACHE_LINE_SIZE_DETECT */
179+ #endif /* CONFIG_DCACHE_LINE_SIZE_DETECT || __DOXYGEN__ */
180180
181- #endif /* CONFIG_DCACHE */
181+ #endif /* CONFIG_DCACHE || __DOXYGEN__ */
182182
183- #if defined(CONFIG_ICACHE )
183+ #if defined(CONFIG_ICACHE ) || defined( __DOXYGEN__ )
184184
185185/**
186186 * @brief Enable the i-cache
@@ -311,7 +311,7 @@ int arch_icache_flush_and_invd_range(void *addr, size_t size);
311311#define cache_instr_flush_and_invd_range (addr , size ) \
312312 arch_icache_flush_and_invd_range(addr, size)
313313
314- #if defined(CONFIG_ICACHE_LINE_SIZE_DETECT )
314+ #if defined(CONFIG_ICACHE_LINE_SIZE_DETECT ) || defined( __DOXYGEN__ )
315315
316316/**
317317 *
@@ -331,9 +331,9 @@ size_t arch_icache_line_size_get(void);
331331
332332#define cache_instr_line_size_get arch_icache_line_size_get
333333
334- #endif /* CONFIG_ICACHE_LINE_SIZE_DETECT */
334+ #endif /* CONFIG_ICACHE_LINE_SIZE_DETECT || __DOXYGEN__ */
335335
336- #endif /* CONFIG_ICACHE */
336+ #endif /* CONFIG_ICACHE || __DOXYGEN__ */
337337
338338/**
339339 * @}
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