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Felipe Nevesnashif
Felipe Neves
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interrupt-controller: intc_esp32c3: make logs optional
Allowing cleaner debug experience and preventing unwanted outputs during debug. Signed-off-by: Felipe Neves <[email protected]>
1 parent 16be75b commit 949a6a8

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-70
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‎drivers/interrupt_controller/Kconfig.esp32c3‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,3 +8,13 @@ config INTC_ESP32C3
88
help
99
Enables the esp32c3 interrupt controller driver to handle ISR
1010
management at SoC level.
11+
12+
config INTC_ESP32C3_DECISIONS_LOG
13+
bool "Enables Espressif's interrupt allocator logging"
14+
depends on INTC_ESP32C3
15+
select LOG
16+
help
17+
Enable this option to visualize information on decisions made by the
18+
interrupt allocator. This has no impact on the interrupt allocator usage
19+
but may be valuable for debugging purposes. When enabled, messages are
20+
print to the serial console.

‎drivers/interrupt_controller/intc_esp32c3.c‎

Lines changed: 18 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,17 @@
2121
#include <logging/log.h>
2222
LOG_MODULE_REGISTER(intc_esp32c3, CONFIG_LOG_DEFAULT_LEVEL);
2323

24+
/*
25+
* Define this to debug the choices made when allocating the interrupt. This leads to much debugging
26+
* output within a critical region, which can lead to weird effects like e.g. the interrupt watchdog
27+
* being triggered, that is why it is separate from the normal LOG* scheme.
28+
*/
29+
#ifdef CONFIG_INTC_ESP32C3_DECISIONS_LOG
30+
# define INTC_LOG(...) LOG_INF(__VA_ARGS__)
31+
#else
32+
# define INTC_LOG(...) do {} while (0)
33+
#endif
34+
2435
#define ESP32C3_INTC_DEFAULT_PRIORITY 15
2536
#define ESP32C3_INTC_DEFAULT_THRESHOLD 1
2637
#define ESP32C3_INTC_DISABLED_SLOT 31
@@ -37,7 +48,7 @@ static void esp_intr_default_isr(const void *arg)
3748
__asm__ volatile("csrr %0, mcause" : "=r" (mcause));
3849
mcause &= SOC_MCAUSE_EXP_MASK;
3950

40-
LOG_DBG("Spurious interrupt, mcause: %ld, source %d", mcause, soc_intr_get_next_source());
51+
INTC_LOG("Spurious interrupt, mcause: %ld, source %d", mcause, soc_intr_get_next_source());
4152
}
4253

4354
static uint32_t esp_intr_find_irq_for_source(uint32_t source)
@@ -48,13 +59,13 @@ static uint32_t esp_intr_find_irq_for_source(uint32_t source)
4859
uint32_t irq = (source / ESP32C3_INTC_SRCS_PER_IRQ);
4960

5061
if (irq > ESP32C3_INTC_AVAILABLE_IRQS) {
51-
LOG_DBG("Clamping the source: %d no more IRQs available", source);
62+
INTC_LOG("Clamping the source: %d no more IRQs available", source);
5263
irq = ESP32C3_INTC_AVAILABLE_IRQS;
5364
} else if (irq == 0) {
5465
irq = 1;
5566
}
5667

57-
LOG_DBG("Found IRQ: %d for source: %d", irq, source);
68+
INTC_LOG("Found IRQ: %d for source: %d", irq, source);
5869

5970
return irq;
6071
}
@@ -118,7 +129,7 @@ int esp_intr_alloc(int source,
118129
esp_intr_enabled_mask[1] |= (1 << (source - 32));
119130
}
120131

121-
LOG_DBG("Enabled isrs -- 0: 0x%X -- 1: 0x%X",
132+
INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X",
122133
esp_intr_enabled_mask[0], esp_intr_enabled_mask[1]);
123134

124135
irq_unlock(key);
@@ -145,7 +156,7 @@ int esp_intr_disable(int source)
145156
esp_intr_enabled_mask[1] &= ~(1 << (source - 32));
146157
}
147158

148-
LOG_DBG("Enabled isrs -- 0: 0x%X -- 1: 0x%X",
159+
INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X",
149160
esp_intr_enabled_mask[0], esp_intr_enabled_mask[1]);
150161

151162
irq_unlock(key);
@@ -171,7 +182,7 @@ int esp_intr_enable(int source)
171182
esp_intr_enabled_mask[1] |= (1 << (source - 32));
172183
}
173184

174-
LOG_DBG("Enabled isrs -- 0: 0x%X -- 1: 0x%X",
185+
INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X",
175186
esp_intr_enabled_mask[0], esp_intr_enabled_mask[1]);
176187

177188
irq_enable(irq);
@@ -182,7 +193,7 @@ int esp_intr_enable(int source)
182193

183194
uint32_t esp_intr_get_enabled_intmask(int status_mask_number)
184195
{
185-
LOG_DBG("Enabled isrs -- 0: 0x%X -- 1: 0x%X",
196+
INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X",
186197
esp_intr_enabled_mask[0], esp_intr_enabled_mask[1]);
187198

188199
if (status_mask_number == 0) {

‎include/drivers/interrupt_controller/intc_esp32c3.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,6 @@
1313
/*
1414
* Interrupt allocation flags - These flags can be used to specify
1515
* which interrupt qualities the code calling esp_intr_alloc* needs.
16-
*
1716
*/
1817

1918
/* Keep the LEVELx values as they are here; they match up with (1<<level) */

‎include/dt-bindings/interrupt-controller/esp-esp32c3-intmux.h‎

Lines changed: 62 additions & 62 deletions
Original file line numberDiff line numberDiff line change
@@ -7,67 +7,67 @@
77
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C3_INTMUX_H_
88
#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C3_INTMUX_H_
99

10-
#define WIFI_MAC_INTR_SOURCE 0 /**< interrupt of WiFi MAC, level*/
11-
#define WIFI_MAC_NMI_SOURCE 1 /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
12-
#define WIFI_PWR_INTR_SOURCE 2 /**< */
13-
#define WIFI_BB_INTR_SOURCE 3 /**< interrupt of WiFi BB, level, we can do some calibartion*/
14-
#define BT_MAC_INTR_SOURCE 4 /**< will be cancelled*/
15-
#define BT_BB_INTR_SOURCE 5 /**< interrupt of BT BB, level*/
16-
#define BT_BB_NMI_SOURCE 6 /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
17-
#define RWBT_INTR_SOURCE 7 /**< interrupt of RWBT, level*/
18-
#define RWBLE_INTR_SOURCE 8 /**< interrupt of RWBLE, level*/
19-
#define RWBT_NMI_SOURCE 9 /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/
20-
#define RWBLE_NMI_SOURCE 10 /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/
21-
#define I2C_MASTER_SOURCE 11 /**< interrupt of I2C Master, level*/
22-
#define SLC0_INTR_SOURCE 12 /**< interrupt of SLC0, level*/
23-
#define SLC1_INTR_SOURCE 13 /**< interrupt of SLC1, level*/
24-
#define APB_CTRL_INTR_SOURCE 14 /**< interrupt of APB ctrl, ?*/
25-
#define UHCI0_INTR_SOURCE 15 /**< interrupt of UHCI0, level*/
26-
#define GPIO_INTR_SOURCE 16 /**< interrupt of GPIO, level*/
27-
#define GPIO_NMI_SOURCE 17 /**< interrupt of GPIO, NMI*/
28-
#define SPI1_INTR_SOURCE 18 /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
29-
#define SPI2_INTR_SOURCE 19 /**< interrupt of SPI2, level*/
30-
#define I2S1_INTR_SOURCE 20 /**< interrupt of I2S1, level*/
31-
#define UART0_INTR_SOURCE 21 /**< interrupt of UART0, level*/
32-
#define UART1_INTR_SOURCE 22 /**< interrupt of UART1, level*/
33-
#define LEDC_INTR_SOURCE 23 /**< interrupt of LED PWM, level*/
34-
#define EFUSE_INTR_SOURCE 24 /**< interrupt of efuse, level, not likely to use*/
35-
#define TWAI_INTR_SOURCE 25 /**< interrupt of can, level*/
36-
#define USB_INTR_SOURCE 26 /**< interrupt of USB, level*/
37-
#define RTC_CORE_INTR_SOURCE 27 /**< interrupt of rtc core, level, include rtc watchdog*/
38-
#define RMT_INTR_SOURCE 28 /**< interrupt of remote controller, level*/
39-
#define I2C_EXT0_INTR_SOURCE 29 /**< interrupt of I2C controller1, level*/
40-
#define TIMER1_INTR_SOURCE 30
41-
#define TIMER2_INTR_SOURCE 31
42-
#define TG0_T0_LEVEL_INTR_SOURCE 32 /**< interrupt of TIMER_GROUP0, TIMER0, level*/
43-
#define TG0_WDT_LEVEL_INTR_SOURCE 33 /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/
44-
#define TG1_T0_LEVEL_INTR_SOURCE 34 /**< interrupt of TIMER_GROUP1, TIMER0, level*/
45-
#define TG1_WDT_LEVEL_INTR_SOURCE 35 /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
46-
#define CACHE_IA_INTR_SOURCE 36 /**< interrupt of Cache Invalied Access, LEVEL*/
47-
#define SYSTIMER_TARGET0_EDGE_INTR_SOURCE 37 /**< interrupt of system timer 0, EDGE*/
48-
#define SYSTIMER_TARGET1_EDGE_INTR_SOURCE 38 /**< interrupt of system timer 1, EDGE*/
49-
#define SYSTIMER_TARGET2_EDGE_INTR_SOURCE 39 /**< interrupt of system timer 2, EDGE*/
50-
#define SPI_MEM_REJECT_CACHE_INTR_SOURCE 40 /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/
51-
#define ICACHE_PRELOAD0_INTR_SOURCE 41 /**< interrupt of ICache perload operation, LEVEL*/
52-
#define ICACHE_SYNC0_INTR_SOURCE 42 /**< interrupt of instruction cache sync done, LEVEL*/
53-
#define APB_ADC_INTR_SOURCE 43 /**< interrupt of APB ADC, LEVEL*/
54-
#define DMA_CH0_INTR_SOURCE 44 /**< interrupt of general DMA channel 0, LEVEL*/
55-
#define DMA_CH1_INTR_SOURCE 45 /**< interrupt of general DMA channel 1, LEVEL*/
56-
#define DMA_CH2_INTR_SOURCE 46 /**< interrupt of general DMA channel 2, LEVEL*/
57-
#define RSA_INTR_SOURCE 47 /**< interrupt of RSA accelerator, level*/
58-
#define AES_INTR_SOURCE 48 /**< interrupt of AES accelerator, level*/
59-
#define SHA_INTR_SOURCE 49 /**< interrupt of SHA accelerator, level*/
60-
#define FROM_CPU_INTR0_SOURCE 50 /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
61-
#define FROM_CPU_INTR1_SOURCE 51 /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
62-
#define FROM_CPU_INTR2_SOURCE 52 /**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
63-
#define FROM_CPU_INTR3_SOURCE 53 /**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
64-
#define ASSIST_DEBUG_INTR_SOURCE 54 /**< interrupt of Assist debug module, LEVEL*/
65-
#define DMA_APBPERI_PMS_INTR_SOURCE 55
66-
#define CORE0_IRAM0_PMS_INTR_SOURCE 56
67-
#define CORE0_DRAM0_PMS_INTR_SOURCE 57
68-
#define CORE0_PIF_PMS_INTR_SOURCE 58
69-
#define CORE0_PIF_PMS_SIZE_INTR_SOURCE 59
70-
#define BAK_PMS_VIOLATE_INTR_SOURCE 60
71-
#define CACHE_CORE0_ACS_INTR_SOURCE 61
10+
#define WIFI_MAC_INTR_SOURCE 0
11+
#define WIFI_MAC_NMI_SOURCE 1
12+
#define WIFI_PWR_INTR_SOURCE 2
13+
#define WIFI_BB_INTR_SOURCE 3
14+
#define BT_MAC_INTR_SOURCE 4
15+
#define BT_BB_INTR_SOURCE 5
16+
#define BT_BB_NMI_SOURCE 6
17+
#define RWBT_INTR_SOURCE 7
18+
#define RWBLE_INTR_SOURCE 8
19+
#define RWBT_NMI_SOURCE 9
20+
#define RWBLE_NMI_SOURCE 10
21+
#define I2C_MASTER_SOURCE 11
22+
#define SLC0_INTR_SOURCE 12
23+
#define SLC1_INTR_SOURCE 13
24+
#define APB_CTRL_INTR_SOURCE 14
25+
#define UHCI0_INTR_SOURCE 15
26+
#define GPIO_INTR_SOURCE 16
27+
#define GPIO_NMI_SOURCE 17
28+
#define SPI1_INTR_SOURCE 18
29+
#define SPI2_INTR_SOURCE 19
30+
#define I2S1_INTR_SOURCE 20
31+
#define UART0_INTR_SOURCE 21
32+
#define UART1_INTR_SOURCE 22
33+
#define LEDC_INTR_SOURCE 23
34+
#define EFUSE_INTR_SOURCE 24
35+
#define TWAI_INTR_SOURCE 25
36+
#define USB_INTR_SOURCE 26
37+
#define RTC_CORE_INTR_SOURCE 27
38+
#define RMT_INTR_SOURCE 28
39+
#define I2C_EXT0_INTR_SOURCE 29
40+
#define TIMER1_INTR_SOURCE 30
41+
#define TIMER2_INTR_SOURCE 31
42+
#define TG0_T0_LEVEL_INTR_SOURCE 32
43+
#define TG0_WDT_LEVEL_INTR_SOURCE 33
44+
#define TG1_T0_LEVEL_INTR_SOURCE 34
45+
#define TG1_WDT_LEVEL_INTR_SOURCE 35
46+
#define CACHE_IA_INTR_SOURCE 36
47+
#define SYSTIMER_TARGET0_EDGE_INTR_SOURCE 37
48+
#define SYSTIMER_TARGET1_EDGE_INTR_SOURCE 38
49+
#define SYSTIMER_TARGET2_EDGE_INTR_SOURCE 39
50+
#define SPI_MEM_REJECT_CACHE_INTR_SOURCE 40
51+
#define ICACHE_PRELOAD0_INTR_SOURCE 41
52+
#define ICACHE_SYNC0_INTR_SOURCE 42
53+
#define APB_ADC_INTR_SOURCE 43
54+
#define DMA_CH0_INTR_SOURCE 44
55+
#define DMA_CH1_INTR_SOURCE 45
56+
#define DMA_CH2_INTR_SOURCE 46
57+
#define RSA_INTR_SOURCE 47
58+
#define AES_INTR_SOURCE 48
59+
#define SHA_INTR_SOURCE 49
60+
#define FROM_CPU_INTR0_SOURCE 50
61+
#define FROM_CPU_INTR1_SOURCE 51
62+
#define FROM_CPU_INTR2_SOURCE 52
63+
#define FROM_CPU_INTR3_SOURCE 53
64+
#define ASSIST_DEBUG_INTR_SOURCE 54
65+
#define DMA_APBPERI_PMS_INTR_SOURCE 55
66+
#define CORE0_IRAM0_PMS_INTR_SOURCE 56
67+
#define CORE0_DRAM0_PMS_INTR_SOURCE 57
68+
#define CORE0_PIF_PMS_INTR_SOURCE 58
69+
#define CORE0_PIF_PMS_SIZE_INTR_SOURCE 59
70+
#define BAK_PMS_VIOLATE_INTR_SOURCE 60
71+
#define CACHE_CORE0_ACS_INTR_SOURCE 61
7272

7373
#endif

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