@@ -94,6 +94,7 @@ int gpio_stm32_configure(u32_t *base_addr, int pin, int conf, int altf)
9494 GPIO_TypeDef * gpio = (GPIO_TypeDef * )base_addr ;
9595
9696 int pin_ll = stm32_pinval_get (pin );
97+
9798#ifdef CONFIG_SOC_SERIES_STM32F1X
9899 ARG_UNUSED (altf );
99100
@@ -179,7 +180,7 @@ int gpio_stm32_configure(u32_t *base_addr, int pin, int conf, int altf)
179180
180181 LL_GPIO_SetPinPull (gpio , pin_ll , pupd >> STM32_PUPDR_SHIFT );
181182
182- #endif /* CONFIG_SOC_SERIES_STM32F1X */
183+ #endif /* CONFIG_SOC_SERIES_STM32F1X */
183184
184185 return 0 ;
185186}
@@ -189,7 +190,7 @@ int gpio_stm32_configure(u32_t *base_addr, int pin, int conf, int altf)
189190 */
190191const int gpio_stm32_enable_int (int port , int pin )
191192{
192- #if defined(CONFIG_SOC_SERIES_STM32F2X ) || \
193+ #if defined(CONFIG_SOC_SERIES_STM32F2X ) || \
193194 defined(CONFIG_SOC_SERIES_STM32F3X ) || \
194195 defined(CONFIG_SOC_SERIES_STM32F4X ) || \
195196 defined(CONFIG_SOC_SERIES_STM32F7X ) || \
@@ -282,7 +283,7 @@ static int gpio_stm32_config(struct device *dev, int access_op,
282283
283284 if ((flags & GPIO_INT_DOUBLE_EDGE ) != 0 ) {
284285 edge = STM32_EXTI_TRIG_RISING |
285- STM32_EXTI_TRIG_FALLING ;
286+ STM32_EXTI_TRIG_FALLING ;
286287 } else if ((flags & GPIO_INT_ACTIVE_HIGH ) != 0 ) {
287288 edge = STM32_EXTI_TRIG_RISING ;
288289 } else {
@@ -411,7 +412,7 @@ static int gpio_stm32_init(struct device *device)
411412 device_get_binding (STM32_CLOCK_CONTROL_NAME );
412413
413414 if (clock_control_on (clk ,
414- (clock_control_subsys_t * ) & cfg -> pclken ) != 0 ) {
415+ (clock_control_subsys_t * )& cfg -> pclken ) != 0 ) {
415416 return - EIO ;
416417 }
417418
@@ -427,36 +428,35 @@ static int gpio_stm32_init(struct device *device)
427428 LL_APB1_GRP1_DisableClock (LL_APB1_GRP1_PERIPH_PWR );
428429 }
429430 }
430- #endif /* PWR_CR2_IOSV */
431+ #endif /* PWR_CR2_IOSV */
431432
432433 return 0 ;
433434}
434435
435436
436437#define GPIO_DEVICE_INIT (__name , __suffix , __base_addr , __port , __cenr , __bus ) \
437- static const struct gpio_stm32_config gpio_stm32_cfg_## __suffix = { \
438- .base = (u32_t *)__base_addr, \
439- .port = __port, \
440- .pclken = { .bus = __bus, .enr = __cenr } \
441- }; \
442- static struct gpio_stm32_data gpio_stm32_data_## __suffix; \
443- DEVICE_AND_API_INIT(gpio_stm32_## __suffix, \
444- __name, \
445- gpio_stm32_init, \
446- &gpio_stm32_data_## __suffix, \
447- &gpio_stm32_cfg_## __suffix, \
448- POST_KERNEL, \
449- CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
450- &gpio_stm32_driver);
451-
452-
453- #define GPIO_DEVICE_INIT_STM32 (__suffix , __SUFFIX ) \
454- GPIO_DEVICE_INIT(DT_GPIO_STM32_GPIO##__SUFFIX##_LABEL, \
455- __suffix, \
456- DT_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS, \
457- STM32_PORT##__SUFFIX, \
458- DT_GPIO_STM32_GPIO##__SUFFIX##_CLOCK_BITS, \
459- DT_GPIO_STM32_GPIO##__SUFFIX##_CLOCK_BUS)
438+ static const struct gpio_stm32_config gpio_stm32_cfg_## __suffix = { \
439+ .base = (u32_t *)__base_addr, \
440+ .port = __port, \
441+ .pclken = { .bus = __bus, .enr = __cenr } \
442+ }; \
443+ static struct gpio_stm32_data gpio_stm32_data_## __suffix; \
444+ DEVICE_AND_API_INIT(gpio_stm32_## __suffix, \
445+ __name, \
446+ gpio_stm32_init, \
447+ &gpio_stm32_data_## __suffix, \
448+ &gpio_stm32_cfg_## __suffix, \
449+ POST_KERNEL, \
450+ CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
451+ &gpio_stm32_driver)
452+
453+ #define GPIO_DEVICE_INIT_STM32 (__suffix , __SUFFIX ) \
454+ GPIO_DEVICE_INIT(DT_GPIO_STM32_GPIO##__SUFFIX##_LABEL, \
455+ __suffix, \
456+ DT_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS, \
457+ STM32_PORT##__SUFFIX, \
458+ DT_GPIO_STM32_GPIO##__SUFFIX##_CLOCK_BITS, \
459+ DT_GPIO_STM32_GPIO##__SUFFIX##_CLOCK_BUS)
460460
461461#ifdef CONFIG_GPIO_STM32_PORTA
462462GPIO_DEVICE_INIT_STM32 (a , A );
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