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dabekjakubnashif
dabekjakub
authored and
nashif
committed
memory manager: refactor
Separate definitions from function code by creating header file for statics managment. Signed-off-by: Jakub Dabek <[email protected]>
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-86
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2 files changed

+95
-86
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‎drivers/mm/mm_drv_intel_adsp.h‎

Lines changed: 88 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,88 @@
1+
/*
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* Copyright (c) 2022 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
6+
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/**
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* @file
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* @brief Header for agregating all defines for mm
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*
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*/
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#ifndef ZEPHYR_DRIVERS_SYSTEM_MM_DRV_INTEL_MTL_
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#define ZEPHYR_DRIVERS_SYSTEM_MM_DRV_INTEL_MTL_
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15+
#define DT_DRV_COMPAT intel_adsp_mtl_tlb
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17+
#include <zephyr/device.h>
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#include <zephyr/kernel.h>
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#include <zephyr/spinlock.h>
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#include <zephyr/sys/__assert.h>
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#include <zephyr/sys/check.h>
22+
#include <zephyr/sys/mem_manage.h>
23+
#include <zephyr/sys/util.h>
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#include <zephyr/drivers/mm/system_mm.h>
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#include <zephyr/sys/mem_blocks.h>
26+
27+
#include <soc.h>
28+
#include <adsp_memory.h>
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30+
#include "mm_drv_common.h"
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32+
DEVICE_MMIO_TOPLEVEL_STATIC(tlb_regs, DT_DRV_INST(0));
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34+
#define TLB_BASE \
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((mm_reg_t)DEVICE_MMIO_TOPLEVEL_GET(tlb_regs))
36+
37+
/*
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* Number of significant bits in the page index (defines the size of
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* the table)
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*/
41+
#define TLB_PADDR_SIZE DT_INST_PROP(0, paddr_size)
42+
#define TLB_EXEC_BIT BIT(DT_INST_PROP(0, exec_bit_idx))
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#define TLB_WRITE_BIT BIT(DT_INST_PROP(0, write_bit_idx))
44+
45+
#define TLB_ENTRY_NUM (1 << TLB_PADDR_SIZE)
46+
#define TLB_PADDR_MASK ((1 << TLB_PADDR_SIZE) - 1)
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#define TLB_ENABLE_BIT BIT(TLB_PADDR_SIZE)
48+
49+
/* This is used to translate from TLB entry back to physical address. */
50+
/* base address of TLB table */
51+
#define TLB_PHYS_BASE \
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(((L2_SRAM_BASE / CONFIG_MM_DRV_PAGE_SIZE) & ~TLB_PADDR_MASK) * CONFIG_MM_DRV_PAGE_SIZE)
53+
#define HPSRAM_SEGMENTS(hpsram_ebb_quantity) \
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((ROUND_DOWN((hpsram_ebb_quantity) + 31u, 32u) / 32u) - 1u)
55+
56+
#define L2_SRAM_PAGES_NUM (L2_SRAM_SIZE / CONFIG_MM_DRV_PAGE_SIZE)
57+
#define MAX_EBB_BANKS_IN_SEGMENT 32
58+
#define SRAM_BANK_SIZE (128 * 1024)
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#define L2_SRAM_BANK_NUM (L2_SRAM_SIZE / SRAM_BANK_SIZE)
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#define IS_BIT_SET(value, idx) ((value) & (1 << (idx)))
61+
62+
/* size of TLB table */
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#define TLB_SIZE DT_REG_SIZE_BY_IDX(DT_INST(0, intel_adsp_mtl_tlb), 0)
64+
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/**
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* Calculate TLB entry based on physical address.
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*
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* @param pa Page-aligned virutal address.
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* @return TLB entry value.
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*/
71+
static inline uint16_t pa_to_tlb_entry(uintptr_t pa)
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{
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return (((pa) / CONFIG_MM_DRV_PAGE_SIZE) & TLB_PADDR_MASK);
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}
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/**
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* Calculate physical address based on TLB entry.
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*
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* @param tlb_entry TLB entry value.
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* @return physcial address pointer.
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*/
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static inline uintptr_t tlb_entry_to_pa(uint16_t tlb_entry)
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{
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return ((((tlb_entry) & TLB_PADDR_MASK) *
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CONFIG_MM_DRV_PAGE_SIZE) + TLB_PHYS_BASE);
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}
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#endif /* ZEPHYR_DRIVERS_SYSTEM_MM_DRV_INTEL_MTL_ */

‎drivers/mm/mm_drv_intel_adsp_mtl_tlb.c‎

Lines changed: 7 additions & 86 deletions
Original file line numberDiff line numberDiff line change
@@ -20,71 +20,16 @@
2020
* are untouched.
2121
*/
2222

23-
#define DT_DRV_COMPAT intel_adsp_mtl_tlb
24-
25-
#include <zephyr/device.h>
26-
#include <zephyr/kernel.h>
27-
#include <zephyr/spinlock.h>
28-
#include <zephyr/sys/__assert.h>
29-
#include <zephyr/sys/check.h>
30-
#include <zephyr/sys/mem_manage.h>
31-
#include <zephyr/sys/util.h>
32-
#include <zephyr/drivers/mm/system_mm.h>
33-
#include <zephyr/sys/mem_blocks.h>
34-
35-
#include <soc.h>
36-
#include <adsp_memory.h>
23+
#include "mm_drv_intel_adsp.h"
3724

3825
#include <zephyr/drivers/mm/mm_drv_intel_adsp_mtl_tlb.h>
39-
#include "mm_drv_common.h"
40-
41-
DEVICE_MMIO_TOPLEVEL_STATIC(tlb_regs, DT_DRV_INST(0));
42-
43-
/* base address of TLB table */
44-
#define TLB_BASE \
45-
((mm_reg_t)DEVICE_MMIO_TOPLEVEL_GET(tlb_regs))
46-
47-
/* size of TLB table */
48-
#define TLB_SIZE DT_REG_SIZE_BY_IDX(DT_INST(0, intel_adsp_mtl_tlb), 0)
49-
50-
/*
51-
* Number of significant bits in the page index (defines the size of
52-
* the table)
53-
*/
54-
#define TLB_PADDR_SIZE DT_INST_PROP(0, paddr_size)
55-
#define TLB_EXEC_BIT BIT(DT_INST_PROP(0, exec_bit_idx))
56-
#define TLB_WRITE_BIT BIT(DT_INST_PROP(0, write_bit_idx))
57-
58-
#define TLB_ENTRY_NUM (1 << TLB_PADDR_SIZE)
59-
#define TLB_PADDR_MASK ((1 << TLB_PADDR_SIZE) - 1)
60-
#define TLB_ENABLE_BIT BIT(TLB_PADDR_SIZE)
61-
62-
/* This is used to translate from TLB entry back to physical address. */
63-
#define TLB_PHYS_BASE \
64-
(((L2_SRAM_BASE / CONFIG_MM_DRV_PAGE_SIZE) & ~TLB_PADDR_MASK) * CONFIG_MM_DRV_PAGE_SIZE)
65-
#define HPSRAM_SEGMENTS(hpsram_ebb_quantity) \
66-
((ROUND_DOWN((hpsram_ebb_quantity) + 31u, 32u) / 32u) - 1u)
67-
68-
#define L2_SRAM_PAGES_NUM (L2_SRAM_SIZE / CONFIG_MM_DRV_PAGE_SIZE)
69-
#define MAX_EBB_BANKS_IN_SEGMENT 32
70-
#define SRAM_BANK_SIZE (128 * 1024)
71-
#define L2_SRAM_BANK_NUM (L2_SRAM_SIZE / SRAM_BANK_SIZE)
72-
#define IS_BIT_SET(value, idx) ((value) & (1 << (idx)))
7326

7427
static struct k_spinlock tlb_lock;
7528
extern struct k_spinlock sys_mm_drv_common_lock;
7629

77-
/* references counter to physical pages */
7830
static int hpsram_ref[L2_SRAM_BANK_NUM];
7931

80-
/* declare L2 physical memory block */
81-
SYS_MEM_BLOCKS_DEFINE_WITH_EXT_BUF(
82-
L2_PHYS_SRAM_REGION,
83-
CONFIG_MM_DRV_PAGE_SIZE,
84-
L2_SRAM_PAGES_NUM,
85-
(uint8_t *) L2_SRAM_BASE);
8632

87-
#ifdef CONFIG_MM_DRV_INTEL_ADSP_TLB_REMAP_UNUSED_RAM
8833
/* Define a marker which is placed by the linker script just after
8934
* last explicitly defined section. All .text, .data, .bss and .heap
9035
* sections should be placed before this marker in the memory.
@@ -95,37 +40,13 @@ __attribute__((__section__(".unused_ram_start_marker")))
9540
static int unused_l2_sram_start_marker = 0xba0babce;
9641
#define UNUSED_L2_START_ALIGNED ROUND_UP(POINTER_TO_UINT(&unused_l2_sram_start_marker), \
9742
CONFIG_MM_DRV_PAGE_SIZE)
98-
#else
99-
/* If memory is not going to be remaped (and thus powered off by)
100-
* the driver, just define the unused memory start as the end of
101-
* the memory.
102-
*/
103-
#define UNUSED_L2_START_ALIGNED ROUND_UP((L2_SRAM_BASE + L2_SRAM_SIZE), \
104-
CONFIG_MM_DRV_PAGE_SIZE)
105-
#endif
10643

107-
/**
108-
* Calculate TLB entry based on physical address.
109-
*
110-
* @param pa Page-aligned virutal address.
111-
* @return TLB entry value.
112-
*/
113-
static inline uint16_t pa_to_tlb_entry(uintptr_t pa)
114-
{
115-
return (((pa) / CONFIG_MM_DRV_PAGE_SIZE) & TLB_PADDR_MASK);
116-
}
117-
118-
/**
119-
* Calculate physical address based on TLB entry.
120-
*
121-
* @param tlb_entry TLB entry value.
122-
* @return physcial address pointer.
123-
*/
124-
static inline uintptr_t tlb_entry_to_pa(uint16_t tlb_entry)
125-
{
126-
return ((((tlb_entry) & TLB_PADDR_MASK) *
127-
CONFIG_MM_DRV_PAGE_SIZE) + TLB_PHYS_BASE);
128-
}
44+
/* declare L2 physical memory block */
45+
SYS_MEM_BLOCKS_DEFINE_WITH_EXT_BUF(
46+
L2_PHYS_SRAM_REGION,
47+
CONFIG_MM_DRV_PAGE_SIZE,
48+
L2_SRAM_PAGES_NUM,
49+
(uint8_t *) L2_SRAM_BASE);
12950

13051
/**
13152
* Calculate the index to the TLB table.

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