dts: wch: add all ch32v003 packages

Add support for all ch32v003 packages.

Signed-off-by: Jianxiong Gu <[email protected]>

Author: recalci

boards/wch/ch32v003evt/ch32v003evt.dts

@@ -5,7 +5,7 @@
 
 /dts-v1/;
 
-#include <wch/ch32v0/ch32v003.dtsi>
+#include <wch/ch32v0/ch32v003f4p.dtsi>
 #include "ch32v003evt-pinctrl.dtsi"
 
 / {

dts/riscv/wch/ch32v0/ch32v003.dtsi

@@ -6,26 +6,12 @@
 
 #include <freq.h>
 #include <mem.h>
+#include <wch/qingke-v2.dtsi>
 #include <zephyr/dt-bindings/gpio/gpio.h>
 #include <zephyr/dt-bindings/i2c/i2c.h>
 #include <zephyr/dt-bindings/clock/ch32v00x-clocks.h>
 
 / {
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu0: cpu@0 {
-			device_type = "cpu";
-			compatible = "wch,qingke-v2";
-			reg = <0>;
-			clock-frequency = <DT_FREQ_M(48)>;
-		};
-	};
-
 	clocks {
 		clk_hse: clk-hse {
 			#clock-cells = <0>;
@@ -55,14 +41,9 @@
 	};
 
 	soc {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "simple-bus";
-		ranges;
-
 		sram0: memory@20000000 {
 			compatible = "mmio-sram";
-			reg = <0x20000000 0x800>;
+			reg = <0x20000000 DT_SIZE_K(2)>;
 		};
 
 		flash: flash-controller@40022000 {
@@ -74,51 +55,35 @@
 
 			flash0: flash@0 {
 				compatible = "soc-nv-flash";
-				reg = <0 0x4000>;
+				reg = <0 DT_SIZE_K(16)>;
 			};
 		};
 
-		pfic: interrupt-controller@e000e000 {
-			compatible = "wch,pfic";
-			#address-cells = <0>;
-			#interrupt-cells = <1>;
-			interrupt-controller;
-			reg = <0xe000e000 16>;
-			status = "okay";
-		};
-
-		systick: systimer@e000f000 {
-			compatible = "wch,systick";
-			reg = <0xe000f000 16>;
-			status = "okay";
-			interrupt-parent = <&pfic>;
-			interrupts = <12>;
-		};
-
 		pwr: pwr@40007000 {
 			compatible = "wch,pwr";
-			reg = <0x40007000 16>;
+			reg = <0x40007000 0x10>;
 		};
 
 		pinctrl: pin-controller@40010000 {
 			compatible = "wch,afio";
-			reg = <0x40010000 16>;
+			reg = <0x40010000 0x10>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			status = "okay";
 
 			gpioa: gpio@40010800 {
 				compatible = "wch,gpio";
-				reg = <0x40010800 32>;
+				reg = <0x40010800 0x20>;
 				gpio-controller;
 				#gpio-cells = <2>;
 				ngpios = <8>;
+				gpio-reserved-ranges = <0 1>, <3 5>;
 				clocks = <&rcc CH32V00X_CLOCK_IOPA>;
 			};
 
 			gpioc: gpio@40011000 {
 				compatible = "wch,gpio";
-				reg = <0x40011000 32>;
+				reg = <0x40011000 0x20>;
 				gpio-controller;
 				#gpio-cells = <2>;
 				ngpios = <8>;
@@ -127,7 +92,7 @@
 
 			gpiod: gpio@40011400 {
 				compatible = "wch,gpio";
-				reg = <0x40011400 32>;
+				reg = <0x40011400 0x20>;
 				gpio-controller;
 				#gpio-cells = <2>;
 				ngpios = <8>;
@@ -137,17 +102,21 @@
 
 		usart1: uart@40013800 {
 			compatible = "wch,usart";
-			reg = <0x40013800 16>;
+			reg = <0x40013800 0x10>;
 			clocks = <&rcc CH32V00X_CLOCK_USART1>;
 			interrupt-parent = <&pfic>;
 			interrupts = <32>;
 		};
 
 		rcc: rcc@40021000 {
 			compatible = "wch,rcc";
-			reg = <0x40021000 16>;
+			reg = <0x40021000 0x10>;
 			#clock-cells = <1>;
 			status = "okay";
 		};
 	};
 };
+
+&cpu0 {
+	clock-frequency = <DT_FREQ_M(48)>;
+};

dts/riscv/wch/ch32v0/ch32v003a4m.dtsi

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2024 Michael Hope
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <wch/ch32v0/ch32v003.dtsi>
+
+&gpioc {
+	gpio-reserved-ranges = <5 1>;
+};
+
+&gpiod {
+	gpio-reserved-ranges = <0 1>, <2 2>;
+};

dts/riscv/wch/ch32v0/ch32v003f4p.dtsi

@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2024 Michael Hope
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <wch/ch32v0/ch32v003.dtsi>

dts/riscv/wch/ch32v0/ch32v003f4u.dtsi

@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2024 Michael Hope
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <wch/ch32v0/ch32v003.dtsi>

dts/riscv/wch/ch32v0/ch32v003j4m.dtsi

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2024 Michael Hope
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <wch/ch32v0/ch32v003.dtsi>
+
+&gpioc {
+	gpio-reserved-ranges = <0 1>, <3 1>, <5 3>;
+};
+
+&gpiod {
+	gpio-reserved-ranges = <0 1>, <2 2>, <7 1>;
+};

dts/riscv/wch/qingke-v2.dtsi

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2024 Michael Hope
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "wch,qingke-v2";
+			reg = <0>;
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		pfic: interrupt-controller@e000e000 {
+			compatible = "wch,pfic";
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			reg = <0xe000e000 0x10>;
+			status = "okay";
+		};
+
+		systick: systimer@e000f000 {
+			compatible = "wch,systick";
+			reg = <0xe000f000 0x10>;
+			status = "okay";
+			interrupt-parent = <&pfic>;
+			interrupts = <12>;
+		};
+	};
+};