drivers: dma: siwx91x: Enable scatter-gather transfer support

Implement support for scatter-gather DMA transfers in the siwx917 driver.
This enhancement allows the driver to handle multiple non-contiguous memory
buffers in a single DMA transaction

Signed-off-by: Sai Santhosh Malae <[email protected]>

Author: smalae

drivers/dma/Kconfig.siwx91x

@@ -4,6 +4,15 @@
 config DMA_SILABS_SIWX91X
 	bool "Silabs SiWx91x DMA driver"
 	default y
+	select SYS_MEM_BLOCKS
 	depends on DT_HAS_SILABS_SIWX91X_DMA_ENABLED
 	help
 	  Enable the High Power(HP)/Ultra Low Power(ULP) DMA driver for the Silabs SiWx91x SoC series.
+
+if DMA_SILABS_SIWX91X
+
+config DMA_SILABS_SIWX91X_SG_BUFFER_COUNT
+	int "The maximum allowable number of buffers for scatter-gather transfers"
+	default 30
+
+endif

drivers/dma/dma_silabs_siwx91x.c

@@ -8,20 +8,23 @@
 #include <zephyr/irq.h>
 #include <zephyr/sys/util.h>
 #include <zephyr/sys/sys_io.h>
+#include <zephyr/sys/mem_blocks.h>
 #include <zephyr/device.h>
 #include <zephyr/drivers/dma.h>
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/types.h>
+#include "rsi_rom_udma.h"
 #include "rsi_rom_udma_wrapper.h"
 #include "rsi_udma.h"
 #include "sl_status.h"
 
-#define DT_DRV_COMPAT          silabs_siwx91x_dma
-#define DMA_MAX_TRANSFER_COUNT 1024
-#define DMA_CH_PRIORITY_HIGH   1
-#define DMA_CH_PRIORITY_LOW    0
-#define UDMA_ADDR_INC_NONE     0x03
+#define DT_DRV_COMPAT                    silabs_siwx91x_dma
+#define DMA_MAX_TRANSFER_COUNT           1024
+#define DMA_CH_PRIORITY_HIGH             1
+#define DMA_CH_PRIORITY_LOW              0
+#define UDMA_ADDR_INC_NONE               0x03
+#define UDMA_MODE_PER_ALT_SCATTER_GATHER 0x07
 
 LOG_MODULE_REGISTER(si91x_dma, CONFIG_DMA_LOG_LEVEL);
 
@@ -31,8 +34,9 @@ enum {
 };
 
 struct dma_siwx91x_channel_info {
-	dma_callback_t dma_callback; /* User callback */
-	void *cb_data;               /* User callback data */
+	dma_callback_t dma_callback;        /* User callback */
+	void *cb_data;                      /* User callback data */
+	RSI_UDMA_DESC_T *sg_desc_addr_info; /* Scatter-Gather table start address */
 };
 
 struct dma_siwx91x_config {
@@ -48,6 +52,7 @@ struct dma_siwx91x_data {
 	struct dma_context dma_ctx;
 	UDMA_Channel_Info *chan_info;
 	struct dma_siwx91x_channel_info *zephyr_channel_info;
+	struct sys_mem_blocks *dma_desc_pool; /* Pointer to the memory pool for DMA descriptor */
 	RSI_UDMA_DATACONTEXT_T udma_handle;  /* Buffer to store UDMA handle
 					      * related information
 					      */
@@ -104,8 +109,158 @@ static int siwx91x_addr_adjustment(uint32_t adjustment)
 	}
 }
 
-static int siwx91x_channel_config(const struct device *dev, RSI_UDMA_HANDLE_T udma_handle,
+/* Sets up the scatter-gather descriptor table for a DMA transfer */
+static int siwx91x_sg_fill_desc(RSI_UDMA_DESC_T *descs, const struct dma_config *config_zephyr)
+{
+	const struct dma_block_config *block_addr = config_zephyr->head_block;
+	RSI_UDMA_CHA_CONFIG_DATA_T *cfg_91x;
+
+	for (int i = 0; i < config_zephyr->block_count; i++) {
+		sys_write32((uint32_t)&descs[i].vsUDMAChaConfigData1, (mem_addr_t)&cfg_91x);
+
+		if (siwx91x_addr_adjustment(block_addr->source_addr_adj) == UDMA_ADDR_INC_NONE) {
+			descs[i].pSrcEndAddr = (void *)block_addr->source_address;
+		} else {
+			descs[i].pSrcEndAddr = (void *)(block_addr->source_address +
+							(block_addr->block_size -
+							 config_zephyr->source_burst_length));
+		}
+		if (siwx91x_addr_adjustment(block_addr->dest_addr_adj) == UDMA_ADDR_INC_NONE) {
+			descs[i].pDstEndAddr = (void *)block_addr->dest_address;
+		} else {
+			descs[i].pDstEndAddr = (void *)(block_addr->dest_address +
+							(block_addr->block_size -
+							 config_zephyr->dest_burst_length));
+		}
+
+		cfg_91x->srcSize = siwx91x_burst_length(config_zephyr->source_burst_length);
+		cfg_91x->dstSize = siwx91x_burst_length(config_zephyr->dest_burst_length);
+
+		/* Calculate the number of DMA transfers required */
+		if (block_addr->block_size / config_zephyr->source_burst_length >
+		    DMA_MAX_TRANSFER_COUNT) {
+			return -EINVAL;
+		}
+
+		cfg_91x->totalNumOfDMATrans =
+			block_addr->block_size / config_zephyr->source_burst_length - 1;
+
+		/* Set the transfer type based on whether it is a peripheral request */
+		if (siwx91x_transfer_direction(config_zephyr->channel_direction) ==
+		    TRANSFER_TO_OR_FROM_PER) {
+			cfg_91x->transferType = UDMA_MODE_PER_ALT_SCATTER_GATHER;
+		} else {
+			cfg_91x->transferType = UDMA_MODE_MEM_ALT_SCATTER_GATHER;
+		}
+
+		cfg_91x->rPower = ARBSIZE_1;
+
+		if (siwx91x_addr_adjustment(block_addr->source_addr_adj) < 0 ||
+		    siwx91x_addr_adjustment(block_addr->dest_addr_adj) < 0) {
+			return -EINVAL;
+		}
+
+		if (siwx91x_addr_adjustment(block_addr->source_addr_adj) == UDMA_ADDR_INC_NONE) {
+			cfg_91x->srcInc = UDMA_SRC_INC_NONE;
+		} else {
+			cfg_91x->srcInc = siwx91x_burst_length(config_zephyr->source_burst_length);
+		}
+
+		if (siwx91x_addr_adjustment(block_addr->dest_addr_adj) == UDMA_ADDR_INC_NONE) {
+			cfg_91x->dstInc = UDMA_DST_INC_NONE;
+		} else {
+			cfg_91x->dstInc = siwx91x_burst_length(config_zephyr->dest_burst_length);
+		}
+
+		/* Move to the next block */
+		block_addr = block_addr->next_block;
+	}
+
+	if (block_addr != NULL) {
+		/* next_block address for last block must be null */
+		return -EINVAL;
+	}
+
+	/* Set the transfer type for the last descriptor */
+	switch (siwx91x_transfer_direction(config_zephyr->channel_direction)) {
+	case TRANSFER_TO_OR_FROM_PER:
+		descs[config_zephyr->block_count - 1].vsUDMAChaConfigData1.transferType =
+			UDMA_MODE_BASIC;
+		break;
+	case TRANSFER_MEM_TO_MEM:
+		descs[config_zephyr->block_count - 1].vsUDMAChaConfigData1.transferType =
+			UDMA_MODE_AUTO;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/* Configure DMA for scatter-gather transfer */
+static int siwx91x_sg_chan_config(const struct device *dev, RSI_UDMA_HANDLE_T udma_handle,
 				  uint32_t channel, const struct dma_config *config)
+{
+	const struct dma_siwx91x_config *cfg = dev->config;
+	struct dma_siwx91x_data *data = dev->data;
+	RSI_UDMA_DESC_T *sg_desc_base_addr = NULL;
+	uint8_t transfer_type;
+	int ret;
+
+	ret = siwx91x_transfer_direction(config->channel_direction);
+	if (ret < 0) {
+		return -EINVAL;
+	}
+	transfer_type = ret ? UDMA_MODE_PER_SCATTER_GATHER : UDMA_MODE_MEM_SCATTER_GATHER;
+
+	if (!siwx91x_is_data_width_valid(config->source_data_size) ||
+	    !siwx91x_is_data_width_valid(config->dest_data_size)) {
+		return -EINVAL;
+	}
+
+	if (siwx91x_burst_length(config->source_burst_length) < 0 ||
+	    siwx91x_burst_length(config->dest_burst_length) < 0) {
+		return -EINVAL;
+	}
+
+	/* Request start index for scatter-gather descriptor table */
+	if (sys_mem_blocks_alloc_contiguous(data->dma_desc_pool, config->block_count,
+					    (void **)&sg_desc_base_addr)) {
+		return -EINVAL;
+	}
+
+	if (siwx91x_sg_fill_desc(sg_desc_base_addr, config)) {
+		return -EINVAL;
+	}
+
+	/* This channel information is used to distinguish scatter-gather transfers and
+	 * free the allocated descriptors in sg_transfer_desc_block
+	 */
+	data->chan_info[channel].Cnt = config->block_count;
+	data->zephyr_channel_info[channel].sg_desc_addr_info = sg_desc_base_addr;
+	RSI_UDMA_InterruptClear(udma_handle, channel);
+	RSI_UDMA_ErrorStatusClear(udma_handle);
+
+	if (cfg->reg == UDMA0) {
+		/* UDMA0 is accessible by both TA and M4, so an interrupt should be configured in
+		 * the TA-M4 common register set to signal the TA when UDMA0 is actively in use.
+		 */
+		sys_write32((BIT(channel) | M4SS_UDMA_INTR_SEL), (mem_addr_t)&M4SS_UDMA_INTR_SEL);
+	} else {
+		sys_set_bit((mem_addr_t)&cfg->reg->UDMA_INTR_MASK_REG, channel);
+	}
+
+	sys_write32(BIT(channel), (mem_addr_t)&cfg->reg->CHNL_PRI_ALT_SET);
+	sys_write32(BIT(channel), (mem_addr_t)&cfg->reg->CHNL_REQ_MASK_CLR);
+
+	RSI_UDMA_SetChannelScatterGatherTransfer(udma_handle, channel, config->block_count,
+						 sg_desc_base_addr, transfer_type);
+	return 0;
+}
+
+static int siwx91x_direct_chan_config(const struct device *dev, RSI_UDMA_HANDLE_T udma_handle,
+				      uint32_t channel, const struct dma_config *config)
 {
 	uint32_t dma_transfer_num = config->head_block->block_size / config->source_burst_length;
 	const struct dma_siwx91x_config *cfg = dev->config;
@@ -210,8 +365,20 @@ static int siwx91x_dma_configure(const struct device *dev, uint32_t channel,
 		return -EINVAL;
 	}
 
+	if (config->cyclic || config->complete_callback_en) {
+		/* Cyclic DMA feature and completion callback for each block
+		 * is not supported
+		 */
+		return -EINVAL;
+	}
+
 	/* Configure dma channel for transfer */
-	status = siwx91x_channel_config(dev, udma_handle, channel, config);
+	if (config->head_block->next_block != NULL) {
+		/* Configure DMA for a Scatter-Gather transfer */
+		status = siwx91x_sg_chan_config(dev, udma_handle, channel, config);
+	} else {
+		status = siwx91x_direct_chan_config(dev, udma_handle, channel, config);
+	}
 	if (status) {
 		return status;
 	}
@@ -429,6 +596,20 @@ static void siwx91x_dma_isr(const struct device *dev)
 	/* find_lsb_set() returns 1 indexed value */
 	channel -= 1;
 
+	if (data->zephyr_channel_info[channel].sg_desc_addr_info) {
+		/* A Scatter-Gather transfer is completed, free the allocated descriptors */
+		if (sys_mem_blocks_free_contiguous(
+			    data->dma_desc_pool,
+			    (void *)data->zephyr_channel_info[channel].sg_desc_addr_info,
+			    data->chan_info[channel].Cnt)) {
+			sys_write32(BIT(channel), (mem_addr_t)&cfg->reg->UDMA_DONE_STATUS_REG);
+			goto out;
+		}
+		data->chan_info[channel].Cnt = 0;
+		data->chan_info[channel].Size = 0;
+		data->zephyr_channel_info[channel].sg_desc_addr_info = NULL;
+	}
+
 	if (data->chan_info[channel].Cnt == data->chan_info[channel].Size) {
 		if (data->zephyr_channel_info[channel].dma_callback) {
 			/* Transfer complete, call user callback */
@@ -466,6 +647,8 @@ static DEVICE_API(dma, siwx91x_dma_api) = {
 #define SIWX91X_DMA_INIT(inst)                                                                     \
 	static ATOMIC_DEFINE(dma_channels_atomic_##inst, DT_INST_PROP(inst, dma_channels));        \
 	static UDMA_Channel_Info dma_channel_info_##inst[DT_INST_PROP(inst, dma_channels)];        \
+	SYS_MEM_BLOCKS_DEFINE_STATIC(desc_pool_##inst, sizeof(RSI_UDMA_DESC_T),                    \
+				     CONFIG_DMA_SILABS_SIWX91X_SG_BUFFER_COUNT, 4);                \
 	static struct dma_siwx91x_channel_info                                                     \
 		zephyr_channel_info_##inst[DT_INST_PROP(inst, dma_channels)];                      \
 	static struct dma_siwx91x_data dma_data_##inst = {                                         \
@@ -474,6 +657,7 @@ static DEVICE_API(dma, siwx91x_dma_api) = {
 		.dma_ctx.atomic = dma_channels_atomic_##inst,                                      \
 		.chan_info = dma_channel_info_##inst,                                              \
 		.zephyr_channel_info = zephyr_channel_info_##inst,                                 \
+		.dma_desc_pool = &desc_pool_##inst,                                                \
 	};                                                                                         \
 	static void siwx91x_dma_irq_configure_##inst(void)                                         \
 	{                                                                                          \

tests/drivers/dma/scatter_gather/boards/siwx917_rb4338a.conf

@@ -0,0 +1,2 @@
+CONFIG_DMA_SG_CHANNEL_NR=7
+CONFIG_DMA_SG_XFER_SIZE=4096

tests/drivers/dma/scatter_gather/boards/siwx917_rb4338a.overlay

@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/ {
+	aliases {
+		dma0 = &dma0;
+	};
+};
+&dma0 {
+	status = "okay";
+};