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Tavish Naruka
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soc: ti: add TI Hercules TMS570LC43x SoC
Adds new SoC. Some of the necessary startup code is based on the vendor provides tool (halcogen) and it includes SoC init and some errata handling. That code originally had BSD-3-clause license, so it cannot be part of this commit, and has been moved to TI hal repository (modules/hal/ti). The Halcogen code was mostly adapted to zephyr coding style and the the dependencies were minimized. As for erratas, the included one right now is PLL startup problem errata. We also have CORTEX-R5#7 (ARM ID-780125), but it was not included because: 1. Halcogen code does not implement it 3. This is Cortex R5 errata, Xilinx R5 implementation has this note https://adaptivesupport.amd.com/s/article/65878 Signed-off-by: Tavish Naruka <[email protected]>
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‎dts/arm/ti/tms570.dtsi‎

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/*
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* Copyright (c) 2025 ispace inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <freq.h>
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#include <mem.h>
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#include <arm/armv7-r.dtsi>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-r5";
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reg = <0>;
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status = "okay";
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};
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};
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clocks {
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/*
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* OSC_IN (16 MHZ)
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* -> PLL1 (300 MHz)
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* -> GCLK1 (300 MHz)
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* -> HCLK (150 MHz)
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* -> VCLK (75 MHz)
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* -> RTICLK (75 MHz, divider is bypassed when VCLK is the source)
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*/
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osc_in: osc_in {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <DT_FREQ_M(16)>;
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status = "okay";
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};
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clk_vclk: clk_vclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <DT_FREQ_M(75)>;
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status = "okay";
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};
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clk_rticlk: clk_rticlk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <DT_FREQ_M(75)>;
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status = "okay";
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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sys: sys@ffffff00 {
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reg = <0xffffff00 256>, /* SYS1 */
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<0xffffe100 256>, /* SYS2 */
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<0xffff1000 0x800>, /* PCR1 */
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<0xfcff1000 0x800>, /* PCR2 */
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<0xfff78000 0x800>, /* PCR3 */
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<0xfff87000 0x1000>, /* FCR */
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<0xfffff500 0x100>, /* ESM */
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<0xFFFFFF00 0xfc>, /* SYSBASE */
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<0xFFFFFC98 4>, /* WATCHDOG_STATUS */
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<0xFFFFEC00 44>, /* DCC */
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<0xFFA04000 0x10>; /* POM_CONTROL_BASE */
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};
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sram0: memory@8000000 {
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compatible = "mmio-sram";
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reg = <0x08000000 DT_SIZE_K(512)>;
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};
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flc0: flash_controller@f0000000 {
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compatible = "flash-controller";
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reg = <0xf0000000 0x00480000>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "okay";
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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reg = <0x00000000 DT_SIZE_M(4)>;
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};
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};
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};
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};

‎soc/ti/hercules/CMakeLists.txt‎

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# SPDX-License-Identifier: Apache-2.0
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add_subdirectory(${SOC_NAME})
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zephyr_include_directories(${SOC_NAME})

‎soc/ti/hercules/Kconfig‎

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# Copyright (c) 2025 ispace, inc.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_FAMILY_TI_HERCULES
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rsource "*/Kconfig"
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endif # SOC_FAMILY_TI_HERCULES

‎soc/ti/hercules/Kconfig.defconfig‎

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# Copyright (c) 2025 ispace, inc.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_FAMILY_TI_HERCULES
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rsource "*/Kconfig.defconfig"
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endif # SOC_FAMILY_TI_HERCULES

‎soc/ti/hercules/Kconfig.soc‎

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# Copyright (c) 2025 ispace, inc.
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# SPDX-License-Identifier: Apache-2.0
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config SOC_FAMILY_TI_HERCULES
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bool
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config SOC_FAMILY
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default "ti_hercules" if SOC_FAMILY_TI_HERCULES
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rsource "*/Kconfig.soc"

‎soc/ti/hercules/soc.yml‎

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family:
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- name: ti_hercules
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series:
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- name: ti_tms570
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socs:
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- name: ti_tms570lc43x

‎soc/ti/hercules/ti_tms570lc43x/CMakeLists.txt‎

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# SPDX-License-Identifier: Apache-2.0
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zephyr_library()
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# TMS470 requires the ARM "legacy Word Invariant Addressing big-endian mode"
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zephyr_compile_options(
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-mbe32
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${TOOLCHAIN_C_FLAGS}
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)
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zephyr_ld_options(
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-mbe32
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${TOOLCHAIN_LD_FLAGS}
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)
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zephyr_library_include_directories(
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${ZEPHYR_BASE}/kernel/include
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${ZEPHYR_BASE}/arch/arm/include
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)
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zephyr_include_directories(.)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_r/scripts/linker.ld CACHE INTERNAL "")

‎soc/ti/hercules/ti_tms570lc43x/Kconfig‎

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# Copyright (c) 2025 ispace, inc.
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# SPDX-License-Identifier: Apache-2.0
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config SOC_TI_TMS570LC43X
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select ARM
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select CPU_CORTEX_R5
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select BIG_ENDIAN
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select CPU_HAS_DCLS
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select CPU_HAS_ARM_MPU
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select CPU_HAS_DCACHE
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select CPU_HAS_ICACHE
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select CACHE_MANAGEMENT
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select SOC_RESET_HOOK
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select ARM_CUSTOM_INTERRUPT_CONTROLLER
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select HAS_TMS570_HALCOGEN_CODE
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imply XIP

‎soc/ti/hercules/ti_tms570lc43x/Kconfig.defconfig‎

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# Copyright (c) Copyright (c) 2025 ispace, inc.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_TI_TMS570LC43X
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config SYS_CLOCK_EXISTS
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default n
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config MULTITHREADING
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default n
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config GEN_SW_ISR_TABLE
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default n
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config GEN_ISR_TABLES
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default n
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# launchpad is 16MHz
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,/soc/rti,clock-frequency)
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config NUM_IRQS
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# must be >= the highest interrupt number used
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default 127
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endif # SOC_TI_TMS570LC43X

‎soc/ti/hercules/ti_tms570lc43x/Kconfig.soc‎

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# Copyright (c) 2024 ispace, inc.
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_TI_TMS570
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bool
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select SOC_FAMILY_TI_HERCULES
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help
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TI Hercules family
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config SOC_TI_TMS570LC43X
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bool
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select SOC_SERIES_TI_TMS570
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help
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TI TMS570LC43X
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config HAS_TMS570_HALCOGEN_CODE
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bool
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config SOC_SERIES
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default "ti_tms570" if SOC_SERIES_TI_TMS570
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config SOC
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default "ti_tms570lc43x" if SOC_TI_TMS570LC43X

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