drivers: clock_control: Add clock control driver for sub-clock on Renesas

RA family

Add clock control driver support for sub-clock Renesas RA family

Signed-off-by: Khoa Tran <[email protected]>

Author: khoatranyj

drivers/clock_control/CMakeLists.txt

@@ -42,6 +42,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SMARTBOND           clock_cont
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NUMAKER_SCC         clock_control_numaker_scc.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NXP_S32             clock_control_nxp_s32.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RA_CGC      clock_control_renesas_ra_cgc.c)
+zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RA_SUBCLK   clock_control_renesas_ra_cgc_subclk.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RX_ROOT     clock_control_renesas_rx_root_cgc.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RX_PLL      clock_control_renesas_rx_pll_cgc.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RX_PCLK     clock_control_renesas_rx_pclk_cgc.c)

drivers/clock_control/Kconfig.renesas_ra_cgc

@@ -8,3 +8,14 @@ config CLOCK_CONTROL_RENESAS_RA_CGC
 	depends on HAS_RENESAS_RA_FSP
 	help
 	  Enable support for Renesas RA CGC driver.
+
+if CLOCK_CONTROL_RENESAS_RA_CGC
+
+config CLOCK_CONTROL_RENESAS_RA_SUBCLK
+	bool "Renesas RA sub clock source"
+	default y
+	depends on DT_HAS_RENESAS_RA_CGC_SUBCLK_ENABLED
+	help
+	  Enable Renesas RA sub clock driver
+
+endif

drivers/clock_control/clock_control_renesas_ra_cgc_subclk.c

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT renesas_ra_cgc_subclk
+
+#include <string.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/kernel.h>
+#include <soc.h>
+
+struct clock_control_ra_subclk_cfg {
+	uint32_t rate;
+};
+
+static int clock_control_renesas_ra_subclk_on(const struct device *dev, clock_control_subsys_t sys)
+{
+	ARG_UNUSED(dev);
+	ARG_UNUSED(sys);
+
+	return -ENOTSUP;
+}
+
+static int clock_control_renesas_ra_subclk_off(const struct device *dev, clock_control_subsys_t sys)
+{
+	ARG_UNUSED(dev);
+	ARG_UNUSED(sys);
+
+	return -ENOTSUP;
+}
+
+static int clock_control_renesas_ra_subclk_get_rate(const struct device *dev,
+						    clock_control_subsys_t sys, uint32_t *rate)
+{
+	const struct clock_control_ra_subclk_cfg *config = dev->config;
+
+	ARG_UNUSED(dev);
+	ARG_UNUSED(sys);
+
+	*rate = config->rate;
+	return 0;
+}
+
+static DEVICE_API(clock_control, clock_control_renesas_ra_subclk_api) = {
+	.on = clock_control_renesas_ra_subclk_on,
+	.off = clock_control_renesas_ra_subclk_off,
+	.get_rate = clock_control_renesas_ra_subclk_get_rate,
+};
+
+#define RENESAS_RA_SUBCLK_INIT(idx)                                                                \
+	static const struct clock_control_ra_subclk_cfg clock_control_ra_subclk_cfg##idx = {       \
+		.rate = DT_INST_PROP(idx, clock_frequency),                                        \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(idx, NULL, NULL, NULL, &clock_control_ra_subclk_cfg##idx,            \
+			      PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY,                    \
+			      &clock_control_renesas_ra_subclk_api);
+
+DT_INST_FOREACH_STATUS_OKAY(RENESAS_RA_SUBCLK_INIT);