dts: arm64: imx8mp: add i2c dts nodes

Add I2C dts nodes for imx8mp Cortex-A Core platform.

Signed-off-by: Jiafei Pan <[email protected]>

Author: JiafeiPan

dts/arm64/nxp/nxp_mimx8mp_a53.dtsi

@@ -189,6 +189,78 @@
 			status = "disabled";
 		};
 
+		i2c1: i2c@30a20000 {
+			compatible = "nxp,ii2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x30a20000 0x10000>;
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-parent = <&gic>;
+			clocks = <&ccm IMX_CCM_I2C1_CLK 0 0>;
+			rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@30a30000 {
+			compatible = "nxp,ii2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x30a30000 0x10000>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-parent = <&gic>;
+			clocks = <&ccm IMX_CCM_I2C2_CLK 0 0>;
+			rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@30a40000 {
+			compatible = "nxp,ii2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x30a40000 0x10000>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-parent = <&gic>;
+			clocks = <&ccm IMX_CCM_I2C3_CLK 0 0>;
+			rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>;
+			status = "disabled";
+		};
+
+		i2c4: i2c@30a50000 {
+			compatible = "nxp,ii2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x30a50000 0x10000>;
+			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-parent = <&gic>;
+			clocks = <&ccm IMX_CCM_I2C4_CLK 0 0>;
+			rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>;
+			status = "disabled";
+		};
+
+		i2c5: i2c@30ad0000 {
+			compatible = "nxp,ii2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x30ad0000 0x10000>;
+			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-parent = <&gic>;
+			clocks = <&ccm IMX_CCM_I2C5_CLK 0 0>;
+			rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>;
+			status = "disabled";
+		};
+
+		i2c6: i2c@30ae0000 {
+			compatible = "nxp,ii2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x30ae0000 0x10000>;
+			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-parent = <&gic>;
+			clocks = <&ccm IMX_CCM_I2C6_CLK 0 0>;
+			rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>;
+			status = "disabled";
+		};
+
 		enet: enet@30be0000 {
 			compatible = "nxp,enet1g";
 			reg = <0x30be0000 DT_SIZE_K(64)>;