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Glauber Maroto Ferreiranashif
Glauber Maroto Ferreira
authored and
nashif
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soc: esp32s2: refactor cache and bss initialization
- refactors cache initialization functions by moving it from soc.c and placing it in soc_cache.c - moves SPIRAM's bss zeroing before SPIRAM initialization Signed-off-by: Glauber Maroto Ferreira <[email protected]>
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-60
lines changed

4 files changed

+105
-60
lines changed

‎soc/xtensa/esp32s2/CMakeLists.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,4 +2,5 @@
22

33
zephyr_sources(
44
soc.c
5+
soc_cache.c
56
)

‎soc/xtensa/esp32s2/soc.c‎

Lines changed: 8 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -59,32 +59,7 @@ void __attribute__((section(".iram1"))) __start(void)
5959
* Configure the mode of instruction cache :
6060
* cache size, cache associated ways, cache line size.
6161
*/
62-
cache_size_t cache_size;
63-
cache_ways_t cache_ways;
64-
cache_line_size_t cache_line_size;
65-
66-
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
67-
esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_INVALID,
68-
CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
69-
cache_size = CACHE_SIZE_8KB;
70-
#else
71-
esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,
72-
CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
73-
cache_size = CACHE_SIZE_16KB;
74-
#endif
75-
76-
cache_ways = CACHE_4WAYS_ASSOC;
77-
78-
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B
79-
cache_line_size = CACHE_LINE_SIZE_16B;
80-
#else
81-
cache_line_size = CACHE_LINE_SIZE_32B;
82-
#endif
83-
84-
esp_rom_Cache_Suspend_ICache();
85-
esp_rom_Cache_Set_ICache_Mode(cache_size, cache_ways, cache_line_size);
86-
esp_rom_Cache_Invalidate_ICache_All();
87-
esp_rom_Cache_Resume_ICache(0);
62+
esp_config_instruction_cache_mode();
8863

8964
/*
9065
* If we need use SPIRAM, we should use data cache, or if we want to
@@ -93,36 +68,7 @@ void __attribute__((section(".iram1"))) __start(void)
9368
* line size.
9469
* Enable data cache, so if we don't use SPIRAM, it just works.
9570
*/
96-
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
97-
#if CONFIG_ESP32S2_DATA_CACHE_8KB
98-
esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW,
99-
CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
100-
cache_size = CACHE_SIZE_8KB;
101-
#else
102-
esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW,
103-
CACHE_MEMORY_DCACHE_HIGH, CACHE_MEMORY_INVALID);
104-
cache_size = CACHE_SIZE_16KB;
105-
#endif
106-
#else
107-
#if CONFIG_ESP32S2_DATA_CACHE_8KB
108-
esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,
109-
CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_INVALID);
110-
cache_size = CACHE_SIZE_8KB;
111-
#else
112-
esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,
113-
CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_DCACHE_HIGH);
114-
cache_size = CACHE_SIZE_16KB;
115-
#endif
116-
#endif
117-
118-
cache_ways = CACHE_4WAYS_ASSOC;
119-
#if CONFIG_ESP32S2_DATA_CACHE_LINE_16B
120-
cache_line_size = CACHE_LINE_SIZE_16B;
121-
#else
122-
cache_line_size = CACHE_LINE_SIZE_32B;
123-
#endif
124-
esp_rom_Cache_Set_DCache_Mode(cache_size, cache_ways, cache_line_size);
125-
esp_rom_Cache_Invalidate_DCache_All();
71+
esp_config_data_cache_mode();
12672
esp_rom_Cache_Enable_DCache(0);
12773

12874
#if !CONFIG_BOOTLOADER_ESP_IDF
@@ -165,6 +111,11 @@ void __attribute__((section(".iram1"))) __start(void)
165111
#endif
166112

167113
#if CONFIG_ESP_SPIRAM
114+
115+
memset(&_ext_ram_bss_start,
116+
0,
117+
(&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start));
118+
168119
esp_err_t err = esp_spiram_init();
169120

170121
if (err != ESP_OK) {
@@ -177,10 +128,7 @@ void __attribute__((section(".iram1"))) __start(void)
177128
abort();
178129
}
179130

180-
memset(&_ext_ram_bss_start,
181-
0,
182-
(&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start));
183-
#endif
131+
#endif /* CONFIG_ESP_SPIRAM */
184132

185133
/* Scheduler is not started at this point. Hence, guard functions
186134
* must be initialized after esp_spiram_init_cache which internally

‎soc/xtensa/esp32s2/soc.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -62,4 +62,8 @@ extern uint8_t g_rom_spiflash_dummy_len_plus[];
6262

6363
extern uint32_t esp_rom_g_ticks_per_us_pro;
6464

65+
/* cache initialization functions */
66+
void IRAM_ATTR esp_config_instruction_cache_mode(void);
67+
void IRAM_ATTR esp_config_data_cache_mode(void);
68+
6569
#endif /* __SOC_H__ */

‎soc/xtensa/esp32s2/soc_cache.c‎

Lines changed: 92 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,92 @@
1+
/*
2+
* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#include "soc.h"
8+
9+
/*
10+
* Instruction Cache definitions
11+
*/
12+
#if defined(CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB)
13+
#define ESP32S2_ICACHE_SIZE CACHE_SIZE_8KB
14+
#else
15+
#define ESP32S2_ICACHE_SIZE CACHE_SIZE_16KB
16+
#endif
17+
18+
#if defined(CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B)
19+
#define ESP32S2_ICACHE_LINE_SIZE CACHE_LINE_SIZE_16B
20+
#else
21+
#define ESP32S2_ICACHE_LINE_SIZE CACHE_LINE_SIZE_32B
22+
#endif
23+
24+
/*
25+
* Data Cache definitions
26+
*/
27+
#if defined(CONFIG_ESP32S2_DATA_CACHE_8KB)
28+
#define ESP32S2_DCACHE_SIZE CACHE_SIZE_8KB
29+
#else
30+
#define ESP32S2_DCACHE_SIZE CACHE_SIZE_16KB
31+
#endif
32+
33+
#if defined(CONFIG_ESP32S2_DATA_CACHE_LINE_16B)
34+
#define ESP32S2_DCACHE_LINE_SIZE CACHE_LINE_SIZE_16B
35+
#else
36+
#define ESP32S2_DCACHE_LINE_SIZE CACHE_LINE_SIZE_32B
37+
#endif
38+
39+
void IRAM_ATTR esp_config_instruction_cache_mode(void)
40+
{
41+
cache_size_t cache_size;
42+
cache_ways_t cache_ways;
43+
cache_line_size_t cache_line_size;
44+
45+
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
46+
esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_INVALID,
47+
CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
48+
#else
49+
esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,
50+
CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
51+
#endif
52+
53+
cache_size = ESP32S2_ICACHE_SIZE;
54+
cache_ways = CACHE_4WAYS_ASSOC;
55+
cache_line_size = ESP32S2_ICACHE_LINE_SIZE;
56+
57+
esp_rom_Cache_Suspend_ICache();
58+
esp_rom_Cache_Set_ICache_Mode(cache_size, cache_ways, cache_line_size);
59+
esp_rom_Cache_Invalidate_ICache_All();
60+
esp_rom_Cache_Resume_ICache(0);
61+
}
62+
63+
void IRAM_ATTR esp_config_data_cache_mode(void)
64+
{
65+
cache_size_t cache_size;
66+
cache_ways_t cache_ways;
67+
cache_line_size_t cache_line_size;
68+
69+
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
70+
#if CONFIG_ESP32S2_DATA_CACHE_8KB
71+
esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW,
72+
CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
73+
#else
74+
esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW,
75+
CACHE_MEMORY_DCACHE_HIGH, CACHE_MEMORY_INVALID);
76+
#endif
77+
#else
78+
#if CONFIG_ESP32S2_DATA_CACHE_8KB
79+
esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,
80+
CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_INVALID);
81+
#else
82+
esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,
83+
CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_DCACHE_HIGH);
84+
#endif
85+
#endif
86+
cache_size = ESP32S2_DCACHE_SIZE;
87+
cache_ways = CACHE_4WAYS_ASSOC;
88+
cache_line_size = ESP32S2_DCACHE_LINE_SIZE;
89+
90+
esp_rom_Cache_Set_DCache_Mode(cache_size, cache_ways, cache_line_size);
91+
esp_rom_Cache_Invalidate_DCache_All();
92+
}

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