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soc: ti_k3: Add TI J721E SoC R5
Add initial SoC support for the TI J721E SoC series Cortex-R5 core. TRM for J721e https://www.ti.com/lit/zip/spruil1 File: spruil1c.pdf Signed-off-by: Prashanth S <[email protected]> Signed-off-by: Andrew Davis <[email protected]>
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‎dts/arm/ti/j721e_main_r5.dtsi‎

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/* Copyright (C) 2023 BeagleBoard.org Foundation
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* Copyright (C) 2023 S Prashanth
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* Copyright (c) 2024 Texas Instruments Incorporated
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* Andrew Davis <[email protected]>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <freq.h>
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#include <arm/armv7-r.dtsi>
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#include <zephyr/dt-bindings/interrupt-controller/ti-vim.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-r5";
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reg = <0>;
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};
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};
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atcm: memory@0 {
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device_type = "memory";
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x00000000 DT_SIZE_K(32)>;
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zephyr,memory-region = "ATCM";
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};
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btcm: memory@41010000 {
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device_type = "memory";
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x41010000 DT_SIZE_K(32)>;
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zephyr,memory-region = "BTCM";
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};
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vim: interrupt-controller@ff80000 {
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#address-cells = <1>;
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compatible = "ti,vim";
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reg = <0x0ff80000 0x2800>;
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interrupt-controller;
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#interrupt-cells = <4>; /* {IRQ/FIQ, IRQ_NUM, IRQ_TYPE, IRQ_PRIO} */
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status = "okay";
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};
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pinctrl: pinctrl@11c000 {
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compatible = "ti,k3-pinctrl";
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reg = <0x0011c000 0x2b4>;
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status = "okay";
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};
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uart1: uart@2810000 {
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compatible = "ns16550";
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reg = <0x02810000 0x100>;
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clock-frequency = <48000000>;
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interrupts = <0 159 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&vim>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart2: uart@2820000 {
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compatible = "ns16550";
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reg = <0x02820000 0x100>;
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clock-frequency = <48000000>;
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interrupts = <0 160 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&vim>;
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reg-shift = <2>;
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status = "disabled";
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};
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systick_timer: timer@24c0000 {
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compatible = "ti,am654-timer";
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reg = <0x24c0000 0x70>;
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interrupts = <0 168 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&vim>;
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status = "disabled";
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};
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};

‎include/zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h‎

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#define MUX_MODE_7 7
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#define MUX_MODE_8 8
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#define MUX_MODE_9 9
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#define MUX_MODE_10 10
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#define MUX_MODE_11 11
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#define MUX_MODE_12 12
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#define MUX_MODE_13 13
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#define MUX_MODE_14 14
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#define K3_PINMUX(offset, value, mux_mode) (((offset) & 0x1fff)) ((value) | (mux_mode))
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‎soc/ti/k3/am6x/CMakeLists.txt‎

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@@ -18,4 +18,15 @@ elseif(CONFIG_SOC_SERIES_AM6X_M4)
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endif()
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set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/m4/linker.ld CACHE INTERNAL "")
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elseif(CONFIG_SOC_SERIES_AM6X_R5)
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zephyr_sources(r5/soc.c)
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zephyr_include_directories(r5)
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if(CONFIG_OPENAMP_RSC_TABLE)
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zephyr_linker_section(NAME .resource_table GROUP ROM_REGION NOINPUT)
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zephyr_linker_section_configure(SECTION .resource_table KEEP INPUT ".resource_table*")
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endif()
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set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/r5/linker.ld CACHE INTERNAL "")
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endif()

‎soc/ti/k3/am6x/Kconfig‎

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select MM_TI_RAT
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select SOC_EARLY_INIT_HOOK
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config SOC_SERIES_AM6X_R5
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select ARM
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select CPU_CORTEX_R5
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select CPU_HAS_ARM_MPU
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select ARM_CUSTOM_INTERRUPT_CONTROLLER
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select VIM
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select TI_DM_TIMER
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select OPENAMP_RSC_TABLE
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select UART_NS16550_ACCESS_WORD_ONLY if UART_NS16550
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config SOC_PART_NUMBER
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default "AM6234" if SOC_AM6234_A53
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default "AM6234" if SOC_AM6234_M4
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default "AM6442" if SOC_AM6442_M4
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default "J721e" if SOC_J721E_MAIN_R5F0_0

‎soc/ti/k3/am6x/Kconfig.defconfig‎

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if SOC_SERIES_AM6X
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config KERNEL_ENTRY
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default "_vector_table"
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# Workaround for not being able to have commas in macro arguments
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DT_CHOSEN_Z_FLASH := zephyr,flash
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int
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default 64 if SOC_SERIES_AM6X_M4
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default 280 if SOC_SERIES_AM6X_A53
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default 512 if SOC_SERIES_AM6X_R5
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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int
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default 400000000 if SOC_SERIES_AM6X_M4
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default 200000000 if SOC_SERIES_AM6X_A53
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default 19200000 if SOC_SERIES_AM6X_R5
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config PINCTRL
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default y
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config UART_NS16550_TI_K3
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default y if SOC_SERIES_AM6X_M4
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default y if SOC_SERIES_AM6X_R5
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choice UART_NS16550_VARIANT
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default UART_NS16550_VARIANT_NS16750
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config BUILD_OUTPUT_BIN
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default n if SOC_SERIES_AM6X_M4
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default n if SOC_SERIES_AM6X_R5
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config BUILD_NO_GAP_FILL
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default y if SOC_SERIES_AM6X_M4
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default y if SOC_SERIES_AM6X_R5
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endif # SOC_SERIES_AM6X

‎soc/ti/k3/am6x/Kconfig.soc‎

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help
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Enable support for AM62X M4 Series.
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config SOC_SERIES_AM6X_R5
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bool
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select SOC_SERIES_AM6X
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help
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Enable support for AM6X R5 Series.
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config SOC_AM6234_A53
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bool
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select SOC_SERIES_AM6X_A53
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bool
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select SOC_SERIES_AM6X_M4
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config SOC_J721E_MAIN_R5F0_0
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bool
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select SOC_SERIES_AM6X_R5
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config SOC_SERIES
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default "am6x" if SOC_SERIES_AM6X
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config SOC
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default "am6234" if SOC_AM6234_M4 || SOC_AM6234_A53
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default "am6442" if SOC_AM6442_M4
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default "j721e" if SOC_J721E_MAIN_R5F0_0

‎soc/ti/k3/am6x/r5/linker.ld‎

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/* Copyright (C) 2023 BeagleBoard.org Foundation
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* Copyright (C) 2023 S Prashanth
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/arch/arm/cortex_a_r/scripts/linker.ld>
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SECTIONS
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{
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#ifdef CONFIG_OPENAMP_RSC_TABLE
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SECTION_PROLOGUE(.resource_table,, SUBALIGN(4))
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{
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KEEP(*(.resource_table*))
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} GROUP_LINK_IN(RSC_TABLE)
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#endif
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}

‎soc/ti/k3/am6x/r5/soc.c‎

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/* Copyright (C) 2023 BeagleBoard.org Foundation
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* Copyright (C) 2023 S Prashanth
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <zephyr/fatal.h>
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#include "soc.h"
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unsigned int z_soc_irq_get_active(void)
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{
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return z_vim_irq_get_active();
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}
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void z_soc_irq_eoi(unsigned int irq)
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{
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z_vim_irq_eoi(irq);
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}
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void z_soc_irq_init(void)
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{
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z_vim_irq_init();
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}
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void z_soc_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
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{
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/* Configure interrupt type and priority */
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z_vim_irq_priority_set(irq, prio, flags);
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}
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void z_soc_irq_enable(unsigned int irq)
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{
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/* Enable interrupt */
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z_vim_irq_enable(irq);
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}
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void z_soc_irq_disable(unsigned int irq)
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{
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/* Disable interrupt */
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z_vim_irq_disable(irq);
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}
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int z_soc_irq_is_enabled(unsigned int irq)
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{
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/* Check if interrupt is enabled */
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return z_vim_irq_is_enabled(irq);
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}

‎soc/ti/k3/am6x/r5/soc.h‎

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/* Copyright (C) 2023 BeagleBoard.org Foundation
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* Copyright (C) 2023 S Prashanth
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _TI_K3_J721E_R5_SOC_H_
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#define _TI_K3_J721E_R5_SOC_H_
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#include <zephyr/drivers/interrupt_controller/intc_vim.h>
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#endif /* _TI_K3_J721E_R5_SOC_H_ */

‎soc/ti/k3/soc.yml‎

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- name: am6442
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cpuclusters:
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- name: m4
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- name: j721e
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cpuclusters:
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- name: main_r5f0_0

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