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soc: renesas: Add support for Renesas RZ/V2H R8 core
Add support for Renesas RZ/V2H R8 core Signed-off-by: Tien Nguyen <[email protected]>
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‎soc/renesas/rz/rzv2h/CMakeLists.txt

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@@ -6,5 +6,14 @@ zephyr_include_directories(.)
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if(CONFIG_SOC_R9A09G057H44GBG_CM33)
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zephyr_include_directories(cm33)
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zephyr_sources(cm33/soc.c)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
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elseif(CONFIG_SOC_R9A09G057H44GBG_CR8)
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zephyr_include_directories(cr8)
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zephyr_sources(cr8/soc.c)
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zephyr_sources_ifdef(CONFIG_ARM_MPU cr8/arm_mpu_regions.c)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "")
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endif()

‎soc/renesas/rz/rzv2h/Kconfig

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@@ -10,3 +10,16 @@ config SOC_R9A09G057H44GBG_CM33
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select SOC_EARLY_INIT_HOOK
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select CPU_HAS_FPU
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select ARMV8_M_DSP
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config SOC_R9A09G057H44GBG_CR8
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select ARM
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select CPU_CORTEX_R8
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select ARM_ARCH_TIMER
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select ARM_CUSTOM_INTERRUPT_CONTROLLER
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select HAS_RENESAS_RZ_FSP
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select VFP_DP_D16
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select SOC_EARLY_INIT_HOOK
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select CPU_HAS_ICACHE
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select CPU_HAS_DCACHE

‎soc/renesas/rz/rzv2h/Kconfig.defconfig.rzv2h_cr8

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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_R9A09G057H44GBG_CR8
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config NUM_IRQS
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default 512
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config FPU
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default y
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(div,$(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency),4)
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config FLASH_SIZE
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default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
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config FLASH_BASE_ADDRESS
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default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
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config SYS_CLOCK_EXISTS
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default y
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endif # SOC_R9A09G057H44GBG_CR8

‎soc/renesas/rz/rzv2h/Kconfig.soc

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@@ -22,5 +22,11 @@ config SOC_R9A09G057H44GBG_CM33
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help
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RZ/V2H CM33
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config SOC_R9A09G057H44GBG_CR8
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bool
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select SOC_R9A09G057H44GBG
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help
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RZ/V2H CR8
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config SOC
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default "r9a09g057h44gbg" if SOC_R9A09G057H44GBG

‎soc/renesas/rz/rzv2h/cm33/soc.c

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/* System core clock is set to 200 MHz after reset */
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uint32_t SystemCoreClock = 200000000;
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void *gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES];
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void soc_early_init_hook(void)
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{

‎soc/renesas/rz/rzv2h/cr8/arm_mpu_regions.c

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/arch/arm/mpu/arm_mpu.h>
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/* clang-format off */
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#define MPUTYPE_READ_ONLY \
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{ \
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.rasr = (P_RO_U_RO_Msk \
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| (7 << MPU_RASR_TEX_Pos) \
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| MPU_RASR_C_Msk \
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| MPU_RASR_B_Msk \
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| MPU_RASR_XN_Msk) \
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}
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#define MPUTYPE_READ_ONLY_PRIV \
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{ \
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.rasr = (P_RO_U_RO_Msk \
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| (5 << MPU_RASR_TEX_Pos) \
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| MPU_RASR_B_Msk) \
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}
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#define MPUTYPE_PRIV_WBWACACHE_XN \
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{ \
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.rasr = (P_RW_U_NA_Msk \
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| (5 << MPU_RASR_TEX_Pos) \
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| MPU_RASR_B_Msk \
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| MPU_RASR_XN_Msk) \
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}
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#define MPUTYPE_PRIV_DEVICE \
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{ \
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.rasr = (P_RW_U_NA_Msk \
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| (2 << MPU_RASR_TEX_Pos) \
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| MPU_RASR_XN_Msk \
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| MPU_RASR_B_Msk \
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| MPU_RASR_S_Msk) \
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}
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/* clang-format on */
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extern uint32_t _image_rom_end_order;
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static const struct arm_mpu_region mpu_regions[] = {
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/* clang-format off */
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MPU_REGION_ENTRY("SRAM",
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0x00000000,
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REGION_256M,
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MPUTYPE_PRIV_WBWACACHE_XN),
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MPU_REGION_ENTRY("SRAM",
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0x00000000,
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((uint32_t)&_image_rom_end_order),
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MPUTYPE_READ_ONLY_PRIV),
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MPU_REGION_ENTRY("REGISTERS",
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0x10000000,
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REGION_256M,
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MPUTYPE_PRIV_DEVICE),
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MPU_REGION_ENTRY("FLASH",
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0x20000000,
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REGION_256M,
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MPUTYPE_READ_ONLY),
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/* clang-format on */
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};
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const struct arm_mpu_config mpu_config = {
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.num_regions = ARRAY_SIZE(mpu_regions),
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.mpu_regions = mpu_regions,
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};

‎soc/renesas/rz/rzv2h/cr8/soc.c

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for Renesas RZ/V2H Group
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*/
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#include <bsp_api.h>
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#include <zephyr/init.h>
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#include <zephyr/sys/barrier.h>
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#include <zephyr/drivers/interrupt_controller/gic.h>
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#include <zephyr/irq.h>
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#include <zephyr/cache.h>
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/* System core clock is set to 800 MHz after reset */
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uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
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void *gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES + BSP_CORTEX_VECTOR_TABLE_ENTRIES];
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uint16_t g_current_interrupt_num[32];
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uint8_t g_current_interrupt_pointer;
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void soc_early_init_hook(void)
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{
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bsp_clock_init();
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/* Initialize SystemCoreClock variable. */
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SystemCoreClockUpdate();
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/* Enable caches */
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sys_cache_instr_enable();
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sys_cache_data_enable();
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}
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unsigned int z_soc_irq_get_active(void)
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{
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int intid = arm_gic_get_active();
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if (intid != 1023) {
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g_current_interrupt_num[g_current_interrupt_pointer++] = intid;
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}
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return intid;
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}
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void z_soc_irq_eoi(unsigned int intid)
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{
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if (intid != 1023) {
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g_current_interrupt_pointer--;
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}
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arm_gic_eoi(intid);
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}
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void z_soc_irq_enable(unsigned int irq)
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{
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arm_gic_irq_enable(irq);
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}
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void z_soc_irq_disable(unsigned int irq)
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{
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arm_gic_irq_disable(irq);
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}
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int z_soc_irq_is_enabled(unsigned int irq)
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{
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return arm_gic_irq_is_enabled(irq);
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}
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void z_soc_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
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{
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arm_gic_irq_set_priority(irq, prio, flags);
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}
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void z_soc_irq_init(void)
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{
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g_current_interrupt_pointer = 0;
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}

‎soc/renesas/rz/rzv2h/cr8/soc.h

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_RENESAS_RZV2H_SOC_H_
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#define ZEPHYR_SOC_RENESAS_RZV2H_SOC_H_
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/* Define CMSIS configurations */
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#define __CR_REV 1U
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/* Do not let CMSIS to handle GIC and Timer */
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#define __GIC_PRESENT 0
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#define __TIM_PRESENT 0
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#define __FPU_PRESENT 1
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#endif /* ZEPHYR_SOC_RENESAS_RZV2H_SOC_H_ */

‎soc/renesas/rz/soc.yml

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- name: r9a09g057h44gbg
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cpuclusters:
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- name: cm33
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- name: cr8_0
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- name: rzv2n
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socs:
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- name: r9a09g056n48gbg

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