dts: st: h7: add dmamux1 bindings

Add dmamux1 dts bindings for stm32h7
series. Note that there is no dedicated
clock to enable for dmamux1 so we set the
clock of dma1. This is the way linux handle
this.

Signed-off-by: Shlomi Vaknin <[email protected]>

Author: shlomow

dts/arm/st/h7/stm32h7.dtsi

@@ -712,6 +712,23 @@
 			label = "DMA_2";
 		};
 
+		dmamux1: dmamux@40020800 {
+			compatible = "st,stm32-dmamux";
+			#dma-cells = <4>;
+			reg = <0x40020800 0x400>;
+			interrupts = <102 0>;
+			/* dmamux1 has no dedicated clock, so we enable dma1 clock */
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
+			dma-channels = <16>;
+			dma-generators = <8>;
+			status = "disabled";
+			label = "DMAMUX_1";
+			/*
+			 * dma-requests is different among h7 socs,
+			 * so we set in specific dtsi files
+			 */
+		};
+
 		rng: rng@48021800 {
 			compatible = "st,stm32-rng";
 			reg = <0x48021800 0x400>;

dts/arm/st/h7/stm32h723.dtsi

@@ -22,7 +22,12 @@
 			status = "disabled";
 			label = "UART_9";
 		};
+
+		dmamux1: dmamux@40020800 {
+			dma-requests= <129>;
+		};
 	};
+
 	/* DTCM memory directly coppled to CPU */
 	dtcm: memory@20000000 {
 		compatible = "arm,dtcm";

dts/arm/st/h7/stm32h743.dtsi

@@ -14,7 +14,12 @@
 				erase-block-size = <DT_SIZE_K(128)>;
 			};
 		};
+
+		dmamux1: dmamux@40020800 {
+			dma-requests= <107>;
+		};
 	};
+
 	/* system data RAM accessible over over AXI bus */
 	sram0: memory@24000000 {
 		compatible = "mmio-sram";

dts/arm/st/h7/stm32h745.dtsi

@@ -20,6 +20,10 @@
 				erase-block-size = <DT_SIZE_K(128)>;
 			};
 		};
+
+		dmamux1: dmamux@40020800 {
+			dma-requests= <107>;
+		};
 	};
 	/*
 	* The RAM memories placed here can be used by both cores M4/M7

dts/arm/st/h7/stm32h750.dtsi

@@ -7,6 +7,12 @@
 #include <st/h7/stm32h7.dtsi>
 
 / {
+	soc {
+		dmamux1: dmamux@40020800 {
+			dma-requests= <107>;
+		};
+	};
+
 	/* system data RAM accessible over over AXI bus */
 	sram0: memory@24000000 {
 		compatible = "mmio-sram";