riscv: don't include the secondary CPU boot code when not needed

Linker garbage collection couldn't work due to the explicit reference
in reset.S.

Signed-off-by: Nicolas Pitre <[email protected]>

Author: Nicolas Pitre

arch/riscv/core/CMakeLists.txt

@@ -11,10 +11,13 @@ zephyr_library_sources(
   reboot.c
   reset.S
   switch.S
-  smp.c
   thread.c
 )
 
+if ((CONFIG_MP_MAX_NUM_CPUS GREATER 1) OR (CONFIG_SMP))
+  zephyr_library_sources(smp.c)
+endif ()
+
 zephyr_library_sources_ifdef(CONFIG_DEBUG_COREDUMP coredump.c)
 zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
 zephyr_library_sources_ifdef(CONFIG_RISCV_PMP pmp.c pmp.S)

arch/riscv/core/reset.S

@@ -97,6 +97,7 @@ aa_loop:
 	call _PrepC
 
 boot_secondary_core:
+#if CONFIG_MP_MAX_NUM_CPUS > 1
 	la t0, riscv_cpu_wake_flag
 	lr t0, 0(t0)
 	bne a0, t0, boot_secondary_core
@@ -108,3 +109,6 @@ boot_secondary_core:
 	la t0, riscv_cpu_wake_flag
 	sr zero, 0(t0)
 	j z_riscv_secondary_cpu_init
+#else
+	j loop_unconfigured_cores
+#endif