soc: arm: gigadevice: add support for GD32e10x

Add support for the E10x series.

Signed-off-by: YuLong Yao <[email protected]>

Author: feilongfl

soc/arm/gigadevice/gd32e10x/CMakeLists.txt

@@ -0,0 +1,5 @@
+# Copyright (c) 2021 YuLong Yao <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+zephyr_sources(soc.c)

soc/arm/gigadevice/gd32e10x/Kconfig.defconfig.gd32e103

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+# Copyright (c) 2021 YuLong Yao <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC
+	default "gd32e103"
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
+config NUM_IRQS
+	default 83

soc/arm/gigadevice/gd32e10x/Kconfig.defconfig.series

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+# Copyright (c) 2021 YuLong Yao <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_GD32E10X
+
+source "soc/arm/gigadevice/gd32e10x/Kconfig.defconfig.gd32*"
+
+config SOC_SERIES
+	default "gd32e10x"
+
+endif # SOC_SERIES_GD32E10X

soc/arm/gigadevice/gd32e10x/Kconfig.series

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+# Copyright (c) 2021 YuLong Yao <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_GD32E10X
+	bool "GigaDevice GD32E10X series Cortex-M4F MCU"
+	select ARM
+	select CPU_HAS_FPU
+	select CPU_CORTEX_M4
+	select CPU_CORTEX_M_HAS_SYSTICK
+	select CPU_CORTEX_M_HAS_VTOR
+	select SOC_FAMILY_GD32_ARM
+	select GD32_HAS_AFIO_PINMUX
+	help
+	  Enable support for GigaDevice GD32E10X MCU series

soc/arm/gigadevice/gd32e10x/Kconfig.soc

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+# Copyright (c) 2021 YuLong Yao <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+	prompt "GigaDevice GD32E103 MCU Selection"
+	depends on SOC_SERIES_GD32E10X
+
+	config SOC_GD32E103
+		bool "gd32e103"
+endchoice

soc/arm/gigadevice/gd32e10x/linker.ld

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+/*
+ * Copyright (c) 2021 YuLong Yao <[email protected]>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>

soc/arm/gigadevice/gd32e10x/soc.c

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+/*
+ * Copyright (c) 2021 YuLong Yao <[email protected]>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <device.h>
+#include <init.h>
+#include <soc.h>
+
+static int gd32e10x_soc_init(const struct device *dev)
+{
+	uint32_t key;
+
+	ARG_UNUSED(dev);
+
+	key = irq_lock();
+
+	SystemInit();
+	NMI_INIT();
+
+	irq_unlock(key);
+
+	return 0;
+}
+
+SYS_INIT(gd32e10x_soc_init, PRE_KERNEL_1, 0);

soc/arm/gigadevice/gd32e10x/soc.h

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2021 YuLong Yao <[email protected]>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC_ARM_GIGADEVICE_GD32E10X_SOC_H_
+#define _SOC_ARM_GIGADEVICE_GD32E10X_SOC_H_
+
+#ifndef _ASMLANGUAGE
+
+#include <gd32e10x.h>
+
+#endif /* _ASMLANGUAGE */
+
+#endif /* _SOC_ARM_GIGADEVICE_GD32E10X_SOC_H_ */