|
146 | 146 | pinmux = <MAX32_PINMUX(0, 6, AF5)>; |
147 | 147 | }; |
148 | 148 |
|
| 149 | + /omit-if-no-ref/ spi1a_miso_p0_7: spi1a_miso_p0_7 { |
| 150 | + pinmux = <MAX32_PINMUX(0, 7, AF1)>; |
| 151 | + }; |
| 152 | + |
| 153 | + /omit-if-no-ref/ uart0b_cts_p0_7: uart0b_cts_p0_7 { |
| 154 | + pinmux = <MAX32_PINMUX(0, 7, AF2)>; |
| 155 | + }; |
| 156 | + |
| 157 | + /omit-if-no-ref/ tmr2c_ia_p0_7: tmr2c_ia_p0_7 { |
| 158 | + pinmux = <MAX32_PINMUX(0, 7, AF3)>; |
| 159 | + }; |
| 160 | + |
| 161 | + /omit-if-no-ref/ uart0d_rx_p0_7: uart0d_rx_p0_7 { |
| 162 | + pinmux = <MAX32_PINMUX(0, 7, AF4)>; |
| 163 | + }; |
| 164 | + |
| 165 | + /omit-if-no-ref/ spi1a_mosi_p0_8: spi1a_mosi_p0_8 { |
| 166 | + pinmux = <MAX32_PINMUX(0, 8, AF1)>; |
| 167 | + }; |
| 168 | + |
| 169 | + /omit-if-no-ref/ uart0b_rts_p0_8: uart0b_rts_p0_8 { |
| 170 | + pinmux = <MAX32_PINMUX(0, 8, AF2)>; |
| 171 | + }; |
| 172 | + |
| 173 | + /omit-if-no-ref/ tmr2c_oa_p0_8: tmr2c_oa_p0_8 { |
| 174 | + pinmux = <MAX32_PINMUX(0, 8, AF3)>; |
| 175 | + }; |
| 176 | + |
| 177 | + /omit-if-no-ref/ uart0d_tx_p0_8: uart0d_tx_p0_8 { |
| 178 | + pinmux = <MAX32_PINMUX(0, 8, AF4)>; |
| 179 | + }; |
| 180 | + |
149 | 181 | /omit-if-no-ref/ i2c1a_sda_p0_9: i2c1a_sda_p0_9 { |
150 | 182 | pinmux = <MAX32_PINMUX(0, 9, AF1)>; |
151 | 183 | }; |
|
233 | 265 | /omit-if-no-ref/ ain0_p0_13: ain0_p0_13 { |
234 | 266 | pinmux = <MAX32_PINMUX(0, 13, AF4)>; |
235 | 267 | }; |
| 268 | + |
| 269 | + |
| 270 | + |
| 271 | + /omit-if-no-ref/ pt0a_p0_14: pt0a_p0_14 { |
| 272 | + pinmux = <MAX32_PINMUX(0, 14, AF1)>; |
| 273 | + }; |
| 274 | + |
| 275 | + /omit-if-no-ref/ pt1a_p0_15: pt1a_p0_15 { |
| 276 | + pinmux = <MAX32_PINMUX(0, 15, AF1)>; |
| 277 | + }; |
| 278 | + |
| 279 | + /omit-if-no-ref/ can0b_rx_p0_15: can0b_rx_p0_15 { |
| 280 | + pinmux = <MAX32_PINMUX(0, 15, AF2)>; |
| 281 | + }; |
| 282 | + |
| 283 | + /omit-if-no-ref/ tmr2c_ia_p0_15: tmr2c_ia_p0_15 { |
| 284 | + pinmux = <MAX32_PINMUX(0, 15, AF3)>; |
| 285 | + }; |
| 286 | + |
| 287 | + /omit-if-no-ref/ tmr0d_ia_p0_15: tmr0d_ia_p0_15 { |
| 288 | + pinmux = <MAX32_PINMUX(0, 15, AF4)>; |
| 289 | + }; |
| 290 | + |
| 291 | + /omit-if-no-ref/ pt2a_p0_16: pt2a_p0_16 { |
| 292 | + pinmux = <MAX32_PINMUX(0, 16, AF1)>; |
| 293 | + }; |
| 294 | + |
| 295 | + /omit-if-no-ref/ can0b_tx_p0_16: can0b_tx_p0_16 { |
| 296 | + pinmux = <MAX32_PINMUX(0, 16, AF2)>; |
| 297 | + }; |
| 298 | + |
| 299 | + /omit-if-no-ref/ tmr2c_oa_p0_16: tmr2c_oa_p0_16 { |
| 300 | + pinmux = <MAX32_PINMUX(0, 16, AF3)>; |
| 301 | + }; |
| 302 | + |
| 303 | + /omit-if-no-ref/ tmr0d_oa_p0_16: tmr0d_oa_p0_16 { |
| 304 | + pinmux = <MAX32_PINMUX(0, 16, AF4)>; |
| 305 | + }; |
| 306 | + |
| 307 | + /omit-if-no-ref/ spi1a_sck_p0_17: spi1a_sck_p0_17 { |
| 308 | + pinmux = <MAX32_PINMUX(0, 17, AF1)>; |
| 309 | + }; |
| 310 | + |
| 311 | + /omit-if-no-ref/ adc_trig_c_p0_17: adc_trig_c_p0_17 { |
| 312 | + pinmux = <MAX32_PINMUX(0, 17, AF3)>; |
| 313 | + }; |
| 314 | + |
| 315 | + /omit-if-no-ref/ uart0d_cts_p0_17: uart0d_cts_p0_17 { |
| 316 | + pinmux = <MAX32_PINMUX(0, 17, AF4)>; |
| 317 | + }; |
| 318 | + |
| 319 | + /omit-if-no-ref/ spi1a_ss0_p0_18: spi1a_ss0_p0_18 { |
| 320 | + pinmux = <MAX32_PINMUX(0, 18, AF1)>; |
| 321 | + }; |
| 322 | + |
| 323 | + /omit-if-no-ref/ uart0d_rts_p0_17: uart0d_rts_p0_17 { |
| 324 | + pinmux = <MAX32_PINMUX(0, 18, AF4)>; |
| 325 | + }; |
| 326 | + |
| 327 | + /omit-if-no-ref/ uart0a_rts_p0_19: uart0a_rts_p0_19 { |
| 328 | + pinmux = <MAX32_PINMUX(0, 19, AF1)>; |
| 329 | + }; |
| 330 | + |
| 331 | + /omit-if-no-ref/ tmrt1c_ia_p0_19: tmrt1c_ia_p0_19 { |
| 332 | + pinmux = <MAX32_PINMUX(0, 19, AF3)>; |
| 333 | + }; |
| 334 | + |
| 335 | + /omit-if-no-ref/ uart0a_cts_p0_20: uart0a_cts_p0_20 { |
| 336 | + pinmux = <MAX32_PINMUX(0, 20, AF1)>; |
| 337 | + }; |
| 338 | + |
| 339 | + /omit-if-no-ref/ tmrt1c_oa_p0_20: tmrt1c_oa_p0_20 { |
| 340 | + pinmux = <MAX32_PINMUX(0, 20, AF3)>; |
| 341 | + }; |
236 | 342 | }; |
237 | 343 | }; |
238 | 344 | }; |
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