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arch: riscv: smp: add PLIC-based IPI implementation
Add PLIC-based IPI implementation. Signed-off-by: Yong Cong Sin <[email protected]>
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‎arch/riscv/Kconfig‎

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@@ -41,6 +41,7 @@ choice RISCV_SMP_IPI_IMPL
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prompt "RISC-V SMP IPI implementation"
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depends on SMP
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default RISCV_SMP_IPI_CLINT if DT_HAS_SIFIVE_CLINT0_ENABLED
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default RISCV_SMP_IPI_PLIC if PLIC_SUPPORTS_SOFT_INTERRUPT && PLIC_IRQ_AFFINITY
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default RISCV_SMP_IPI_CUSTOM
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config RISCV_SMP_IPI_CLINT
@@ -49,6 +50,14 @@ config RISCV_SMP_IPI_CLINT
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help
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Use CLINT-based IPI implementation.
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config RISCV_SMP_IPI_PLIC
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bool "PLIC-based IPI"
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depends on PLIC_SUPPORTS_SOFT_INTERRUPT
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depends on PLIC_IRQ_AFFINITY
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depends on !FPU_SHARING # not supported for now
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help
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Use PLIC-based IPI implementation.
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config RISCV_SMP_IPI_CUSTOM
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bool "Custom IPI implementation"
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help

‎arch/riscv/core/CMakeLists.txt‎

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@@ -21,6 +21,7 @@ if (CONFIG_SMP)
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zephyr_library_sources(ipi.c)
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zephyr_library_sources_ifdef(CONFIG_RISCV_SMP_IPI_CLINT ipi_clint.c)
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zephyr_library_sources_ifdef(CONFIG_RISCV_SMP_IPI_PLIC ipi_plic.c)
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endif()
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zephyr_library_sources_ifdef(CONFIG_FPU_SHARING fpu.c fpu.S)

‎arch/riscv/core/ipi_plic.c‎

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/*
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* Copyright (c) 2024 Meta Platforms
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* Copyright (c) 2021 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <ipi.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/interrupt_controller/riscv_plic.h>
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#include <zephyr/kernel.h>
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#include <zephyr/sys/util.h>
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#ifdef CONFIG_FPU_SHARING
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#define FPU_IPI_NODE DT_NODELABEL(fpu_ipi)
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#define FPU_IPI_NUM_IRQS DT_NUM_IRQS(FPU_IPI_NODE)
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#define FPU_IPI_IRQ(n) DT_IRQN_BY_IDX(FPU_IPI_NODE, n + CONFIG_MP_MAX_NUM_CPUS)
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#define FPU_IPI_IRQS_FN(n, _) DT_IRQN_BY_IDX(FPU_IPI_NODE, n)
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static const uint32_t fpu_ipi_irqs[FPU_IPI_NUM_IRQS] = {
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LISTIFY(FPU_IPI_NUM_IRQS, FPU_IPI_IRQS_FN, (,)),
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};
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static ALWAYS_INLINE void send_fpu_ipi(int cpu)
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{
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riscv_plic_irq_set_pending(fpu_ipi_irqs[cpu]);
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}
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static ALWAYS_INLINE bool fpu_ipi_irq_is_pending(int cpu)
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{
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return riscv_plic_irq_is_pending(fpu_ipi_irqs[cpu]);
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}
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static ALWAYS_INLINE void fpu_ipi_irq_clear_pending(int cpu)
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{
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riscv_plic_irq_clear_pending(fpu_ipi_irqs[cpu]);
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}
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static void fpu_ipi_handler(const void *arg)
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{
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ARG_UNUSED(arg);
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/* disable IRQs */
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csr_clear(mstatus, MSTATUS_IEN);
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/* perform the flush */
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arch_flush_local_fpu();
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/*
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* No need to re-enable IRQs here as long as
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* this remains the last case.
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*/
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}
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void arch_flush_fpu_ipi(unsigned int cpu)
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{
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send_fpu_ipi(i);
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}
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/*
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* Make sure there is no pending FPU flush request for this CPU while
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* waiting for a contended spinlock to become available. This prevents
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* a deadlock when the lock we need is already taken by another CPU
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* that also wants its FPU content to be reinstated while such content
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* is still live in this CPU's FPU.
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*/
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void arch_spin_relax(void)
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{
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int cpu = _current_cpu->id;
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if (fpu_ipi_irq_is_pending(cpu)) {
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fpu_ipi_irq_clear_pending(cpu);
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/*
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* We may not be in IRQ context here hence cannot use
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* arch_flush_local_fpu() directly.
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*/
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arch_float_disable(_current_cpu->arch.fpu_owner);
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}
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}
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#define FPU_IPI_IRQ_CONNECT(n, _) \
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IRQ_CONNECT(FPU_IPI_IRQ(n), 1, fpu_ipi_handler, UINT_TO_POINTER(n), 0); \
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irq_enable(FPU_IPI_IRQ(n)); \
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riscv_plic_irq_set_affinity(FPU_IPI_IRQ(n), BIT(n))
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#define fpu_ipi_irqs_setup() LISTIFY(CONFIG_MP_MAX_NUM_CPUS, FPU_IPI_IRQ_CONNECT, (;))
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#else
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#define fpu_ipi_irqs_setup()
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#endif /* CONFIG_FPU_SHARING */
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#define SCHED_IPI_NODE DT_NODELABEL(sched_ipi)
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#define SCHED_IPI_NUM_IRQS DT_NUM_IRQS(SCHED_IPI_NODE)
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#define SCHED_IPI_IRQ(n) DT_IRQN_BY_IDX(SCHED_IPI_NODE, n)
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#define SCHED_IPI_IRQS_FN(n, _) DT_IRQN_BY_IDX(SCHED_IPI_NODE, n)
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static const uint32_t sched_ipi_irqs[SCHED_IPI_NUM_IRQS] = {
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LISTIFY(SCHED_IPI_NUM_IRQS, SCHED_IPI_IRQS_FN, (,)),
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};
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static ALWAYS_INLINE void send_sched_ipi(int cpu)
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{
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riscv_plic_irq_set_pending(sched_ipi_irqs[cpu]);
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}
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void arch_sched_directed_ipi(uint32_t cpu_bitmap)
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{
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unsigned int key = arch_irq_lock();
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unsigned int id = _current_cpu->id;
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unsigned int num_cpus = arch_num_cpus();
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for (unsigned int i = 0; i < num_cpus; i++) {
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if ((i != id) && _kernel.cpus[i].arch.online && ((cpu_bitmap & BIT(i)) != 0)) {
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send_sched_ipi(i);
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}
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}
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arch_irq_unlock(key);
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}
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static void sched_ipi_handler(const void *arg)
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{
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ARG_UNUSED(arg);
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z_sched_ipi();
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}
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#define SCHED_IPI_IRQ_CONNECT(n, _) \
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IRQ_CONNECT(SCHED_IPI_IRQ(n), 1, sched_ipi_handler, UINT_TO_POINTER(n), 0); \
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irq_enable(SCHED_IPI_IRQ(n)); \
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riscv_plic_irq_set_affinity(SCHED_IPI_IRQ(n), BIT(n))
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#define sched_ipi_irqs_setup() LISTIFY(CONFIG_MP_MAX_NUM_CPUS, SCHED_IPI_IRQ_CONNECT, (;))
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int arch_smp_init(void)
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{
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sched_ipi_irqs_setup();
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fpu_ipi_irqs_setup();
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return 0;
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}
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‎boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.dts‎

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@@ -140,6 +140,35 @@
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zephyr,code = <INPUT_KEY_6>;
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};
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};
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sched_ipi: sched_ipi {
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compatible = "zephyr,ipi-plic";
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interrupt-parent = <&plic_sw>;
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interrupts =
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/* sched IPI IRQs */
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<32 1>, /* CPU 0 */
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<33 1>, /* CPU 1 */
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<34 1>, /* CPU 2 */
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<35 1>, /* CPU 3 */
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<36 1>, /* CPU 4 */
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<37 1>, /* CPU 5 */
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<38 1>, /* CPU 6 */
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<39 1>; /* CPU 7 */
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};
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fpu_ipi: fpu_ipi {
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compatible = "zephyr,ipi-plic";
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interrupt-parent = <&plic_sw>;
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interrupts =
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<40 1>, /* CPU 0 */
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<41 1>, /* CPU 1 */
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<42 1>, /* CPU 2 */
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<43 1>, /* CPU 3 */
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<44 1>, /* CPU 4 */
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<45 1>, /* CPU 5 */
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<46 1>, /* CPU 6 */
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<47 1>; /* CPU 7 */
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};
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};
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&l2_cache {

‎dts/bindings/misc/zephyr,ipi-plic.yaml‎

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# Copyright (c) 2024 Meta Platforms
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# SPDX-License-Identifier: Apache-2.0
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description: IPI PLIC pseudo device
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compatible: "zephyr,ipi-plic"
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include: [base.yaml]
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properties:
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interrupt-parent:
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required: true
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interrupts:
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required: true

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