drivers: pinctrl_nrf: Add coresight tpiu pins

Pinctrl needs to set the needed drive and direction of the pins. Also
this later allows automatically setting the clock bit for the traceclk
pin.

Signed-off-by: Karsten Koenig <[email protected]>

Author: karstenkoenig

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi

@@ -138,4 +138,15 @@
 			low-power-enable;
 		};
 	};
+
+	/omit-if-no-ref/ tpiu_default: tpiu_default {
+		group1 {
+			psels = <NRF_PSEL(TPIU_CLOCK, 7, 3)>,
+				<NRF_PSEL(TPIU_DATA0, 7, 4)>,
+				<NRF_PSEL(TPIU_DATA1, 7, 5)>,
+				<NRF_PSEL(TPIU_DATA2, 7, 6)>,
+				<NRF_PSEL(TPIU_DATA3, 7, 7)>;
+			nordic,drive-mode = <NRF_DRIVE_H0H1>;
+		};
+	};
 };

drivers/pinctrl/pinctrl_nrf.c

@@ -557,6 +557,17 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 			input = NRF_GPIO_PIN_INPUT_CONNECT;
 			break;
 #endif /* defined(NRF_PSEL_TWIS) */
+#if DT_HAS_COMPAT_STATUS_OKAY(nordic_coresight_nrf)
+		/* Pin routing is controlled by secure domain, via UICR */
+		case NRF_FUN_TPIU_CLOCK:
+		case NRF_FUN_TPIU_DATA0:
+		case NRF_FUN_TPIU_DATA1:
+		case NRF_FUN_TPIU_DATA2:
+		case NRF_FUN_TPIU_DATA3:
+			dir = NRF_GPIO_PIN_DIR_OUTPUT;
+			input = NRF_GPIO_PIN_INPUT_DISCONNECT;
+			break;
+#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_coresight_nrf) */
 		default:
 			return -ENOTSUP;
 		}

include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h

@@ -187,7 +187,17 @@
 /** TDM MCK */
 #define NRF_FUN_TDM_MCK          77U
 /** SPI master CSN */
-#define NRF_FUN_SPIM_CSN 78U
+#define NRF_FUN_SPIM_CSN         78U
+/** TPIU CLOCK */
+#define NRF_FUN_TPIU_CLOCK       79U
+/** TPIU DATA0 */
+#define NRF_FUN_TPIU_DATA0       80U
+/** TPIU DATA1 */
+#define NRF_FUN_TPIU_DATA1       81U
+/** TPIU DATA2 */
+#define NRF_FUN_TPIU_DATA2       82U
+/** TPIU DATA3 */
+#define NRF_FUN_TPIU_DATA3       83U
 
 /** @} */
 

soc/nordic/common/uicr/gen_periphconf_entries.py

@@ -425,6 +425,14 @@ def lookup_tables_get(soc: Soc) -> SocLookupTables:
                 NrfPsel(fun=NrfFun.IGNORE, port=2, pin=10): Ctrlsel.CAN,
                 NrfPsel(fun=NrfFun.IGNORE, port=2, pin=11): Ctrlsel.CAN,
             },
+            # Coresight (TPIU)
+            0xBF04_0000: {
+                NrfPsel(fun=NrfFun.TPIU_CLOCK, port=7, pin=3): Ctrlsel.TND,
+                NrfPsel(fun=NrfFun.TPIU_DATA0, port=7, pin=4): Ctrlsel.TND,
+                NrfPsel(fun=NrfFun.TPIU_DATA1, port=7, pin=5): Ctrlsel.TND,
+                NrfPsel(fun=NrfFun.TPIU_DATA2, port=7, pin=6): Ctrlsel.TND,
+                NrfPsel(fun=NrfFun.TPIU_DATA3, port=7, pin=7): Ctrlsel.TND,
+            },
         }
     elif soc == Soc.NRF9280:
         ctrlsel_lookup = {

soc/nordic/common/uicr/periphconf/builder.py

@@ -41,6 +41,9 @@
     "nordic,nrf-temp",
     "nordic,nrf-vevif-task-tx",
     "nordic,nrf-vevif-task-rx",
+    # No retention in TDD so permissions can't be set outside of the TDD service
+    "nordic,coresight-nrf",
+    "nordic,nrf-tbm",
 }
 
 # Compatibles of global peripherals that should be assigned to the current core but do not have DMA
@@ -1018,6 +1021,11 @@ class NrfFun(int, enum.Enum):
     TDM_SDOUT = 76
     TDM_MCK = 77
     SPIM_CSN = 78
+    TPIU_CLOCK = 79
+    TPIU_DATA0 = 80
+    TPIU_DATA1 = 81
+    TPIU_DATA2 = 82
+    TPIU_DATA3 = 83
 
     # Value used to ignore the function field and only check (port, pin)
     IGNORE = -1