soc: silabs: Add support for MG22 SoCs

Adds SoC definitions and DTS files for SiLabs EFR32MG22 SoCs

Signed-off-by: James Smith <[email protected]>

Author: loopj

dts/arm/silabs/xg22/efr32mg22.dtsi

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <silabs/xg22/efr32xg22.dtsi>
+
+&radio {
+	bt_hci_silabs: bt_hci_silabs {
+		compatible = "silabs,bt-hci-efr32";
+		status = "disabled";
+	};
+};

dts/arm/silabs/xg22/efr32mg22c224f512gn32.dtsi

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2021 Sateesh Kotapati
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <silabs/xg22/efr32mg22.dtsi>
+#include <mem.h>
+
+/ {
+	soc {
+		compatible = "silabs,efr32mg22c224f512gn32", "silabs,efr32mg22", "silabs,xg22",
+			     "silabs,efr32", "simple-bus";
+		model = "Silicon Labs EFR32MG22C224F512GN32 SoC";
+	};
+};
+
+&flash0 {
+	reg = <0x0 DT_SIZE_K(512)>;
+};
+
+&sram0 {
+	reg = <0x20000000 DT_SIZE_K(32)>;
+};

dts/arm/silabs/xg22/efr32mg22c224f512im32.dtsi

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2021 Sateesh Kotapati
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <silabs/xg22/efr32mg22.dtsi>
+#include <mem.h>
+
+/ {
+	soc {
+		compatible = "silabs,efr32mg22c224f512im32", "silabs,efr32mg22", "silabs,xg22",
+			     "silabs,efr32", "simple-bus";
+		model = "Silicon Labs EFR32MG22C224F512IM32 SoC";
+	};
+};
+
+&flash0 {
+	reg = <0x0 DT_SIZE_K(512)>;
+};
+
+&sram0 {
+	reg = <0x20000000 DT_SIZE_K(32)>;
+};

dts/arm/silabs/xg22/efr32mg22c224f512im40.dtsi

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2021 Sateesh Kotapati
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <silabs/xg22/efr32mg22.dtsi>
+#include <mem.h>
+
+/ {
+	soc {
+		compatible = "silabs,efr32mg22c224f512im40", "silabs,efr32mg22", "silabs,xg22",
+			     "silabs,efr32", "simple-bus";
+		model = "Silicon Labs EFR32MG22C224F512IM40 SoC";
+	};
+};
+
+&flash0 {
+	reg = <0x0 DT_SIZE_K(512)>;
+};
+
+&sram0 {
+	reg = <0x20000000 DT_SIZE_K(32)>;
+};

dts/arm/silabs/xg22/efr32mg22e224f512im32.dtsi

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2021 Sateesh Kotapati
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <silabs/xg22/efr32mg22.dtsi>
+#include <mem.h>
+
+/ {
+	soc {
+		compatible = "silabs,efr32mg22e224f512im32", "silabs,efr32mg22", "silabs,xg22",
+			     "silabs,efr32", "simple-bus";
+		model = "Silicon Labs EFR32MG22E224F512IM32 SoC";
+	};
+};
+
+&flash0 {
+	reg = <0x0 DT_SIZE_K(512)>;
+};
+
+&sram0 {
+	reg = <0x20000000 DT_SIZE_K(32)>;
+};

dts/arm/silabs/xg22/efr32mg22e224f512im40.dtsi

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2021 Sateesh Kotapati
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <silabs/xg22/efr32mg22.dtsi>
+#include <mem.h>
+
+/ {
+	soc {
+		compatible = "silabs,efr32mg22e224f512im40", "silabs,efr32mg22", "silabs,xg22",
+			     "silabs,efr32", "simple-bus";
+		model = "Silicon Labs EFR32MG22E224F512IM40 SoC";
+	};
+};
+
+&flash0 {
+	reg = <0x0 DT_SIZE_K(512)>;
+};
+
+&sram0 {
+	reg = <0x20000000 DT_SIZE_K(32)>;
+};

soc/silabs/silabs_s2/xg22/Kconfig

@@ -12,10 +12,14 @@ config SOC_SILABS_XG22
 	select HAS_SWO
 	select SOC_GECKO_GPIO
 	select SOC_GECKO_CMU
+	select SOC_GECKO_EMU
 	select SOC_GECKO_CORE
 	select SOC_GECKO_DEV_INIT
 	select SOC_GECKO_SE
 	select HAS_PM
 
 config SOC_SERIES_EFR32BG22
 	select SOC_GECKO_HAS_RADIO
+
+config SOC_SERIES_EFR32MG22
+	select SOC_GECKO_HAS_RADIO

soc/silabs/silabs_s2/xg22/Kconfig.soc

@@ -13,12 +13,44 @@ config SOC_SERIES_EFR32BG22
 	help
 	  Silicon Labs EFR32BG22 (Blue Gecko) Series MCU
 
+config SOC_SERIES_EFR32MG22
+	bool
+	select SOC_SILABS_XG22
+	help
+	  Silicon Labs EFR32MG22 (Mighty Gecko) Series MCU
+
 config SOC_PART_NUMBER_EFR32BG22C224F512IM40
 	bool
 	select SOC_SERIES_EFR32BG22
 
+config SOC_EFR32MG22C224F512IM40
+	bool
+	select SOC_SERIES_EFR32MG22
+
+config SOC_EFR32MG22C224F512IM32
+	bool
+	select SOC_SERIES_EFR32MG22
+
+config SOC_EFR32MG22C224F512GN32
+	bool
+	select SOC_SERIES_EFR32MG22
+
+config SOC_EFR32MG22E224F512IM40
+	bool
+	select SOC_SERIES_EFR32MG22
+
+config SOC_EFR32MG22E224F512IM32
+	bool
+	select SOC_SERIES_EFR32MG22
+
 config SOC_SERIES
 	default "efr32bg22" if SOC_SERIES_EFR32BG22
+	default "efr32mg22" if SOC_SERIES_EFR32MG22
 
 config SOC
 	default "efr32bg22c224f512im40" if SOC_PART_NUMBER_EFR32BG22C224F512IM40
+	default "efr32mg22c224f512im40" if SOC_EFR32MG22C224F512IM40
+	default "efr32mg22c224f512im32" if SOC_EFR32MG22C224F512IM32
+	default "efr32mg22c224f512gn32" if SOC_EFR32MG22C224F512GN32
+	default "efr32mg22e224f512im40" if SOC_EFR32MG22E224F512IM40
+	default "efr32mg22e224f512im32" if SOC_EFR32MG22E224F512IM32

soc/silabs/soc.yml

@@ -47,6 +47,13 @@ family:
       - name: efr32bg22
         socs:
           - name: efr32bg22c224f512im40
+      - name: efr32mg22
+        socs:
+          - name: efr32mg22c224f512im40
+          - name: efr32mg22c224f512im32
+          - name: efr32mg22c224f512gn32
+          - name: efr32mg22e224f512im40
+          - name: efr32mg22e224f512im32
       - name: efr32mg24
         socs:
           - name: efr32mg24b220f1536im48

west.yml

@@ -235,7 +235,7 @@ manifest:
       groups:
         - hal
     - name: hal_silabs
-      revision: 295caf37909d2ff01688b1c4bd34c9b3584e8333
+      revision: 13343bccf850eb7b6541f6e71a8d2a880209850b
       path: modules/hal/silabs
       groups:
         - hal