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soburisoburi
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drivers: clock_control: renesas_ra: Adding macros to convert DT values
Adding the macros `RA_CGC_CLK_SRC` and `RA_CGC_CLK_DIV` that derive the BSP clock settings from the DeviceTree node settings. I also define some aliases to fill in the gaps with the BSP naming conventions. Signed-off-by: TOKITA Hiroshi <[email protected]>
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-134
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3 files changed

+51
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lines changed

‎drivers/clock_control/clock_control_renesas_ra_cgc.c‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -90,10 +90,11 @@ static const struct clock_control_driver_api clock_control_reneas_ra_api = {
9090
#define INIT_PCLK(node_id) \
9191
IF_ENABLED(DT_NODE_HAS_COMPAT(node_id, renesas_ra_cgc_pclk), \
9292
(static const struct clock_control_ra_pclk_cfg node_id##_cfg = \
93-
{.clk_src = DT_PROP_OR(node_id, clk_src, \
94-
DT_PROP_OR(DT_PARENT(node_id), sysclock_src, \
95-
RA_CLOCK_SOURCE_DISABLE)), \
96-
.clk_div = DT_PROP_OR(node_id, clk_div, RA_SYS_CLOCK_DIV_1)}; \
93+
{.clk_src = COND_CODE_1( \
94+
DT_NODE_HAS_PROP(node_id, clocks), \
95+
(RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(node_id))), \
96+
(RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_PARENT(node_id))))), \
97+
.clk_div = RA_CGC_CLK_DIV(node_id, div, 1)}; \
9798
DEVICE_DT_DEFINE(node_id, &clock_control_ra_init_pclk, NULL, NULL, \
9899
&node_id##_cfg, PRE_KERNEL_1, \
99100
CONFIG_KERNEL_INIT_PRIORITY_OBJECTS, \

‎include/zephyr/drivers/clock_control/renesas_ra_cgc.h‎

Lines changed: 46 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,52 @@
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#include <zephyr/drivers/clock_control.h>
1010
#include <zephyr/dt-bindings/clock/ra_clock.h>
1111

12+
#define RA_CGC_PROP_HAS_STATUS_OKAY_OR(node_id, prop, default_value) \
13+
COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), (DT_PROP(node_id, prop)), (default_value))
14+
15+
#define RA_CGC_CLK_SRC(node_id) \
16+
COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), \
17+
(UTIL_CAT(BSP_CLOCKS_SOURCE_, DT_NODE_FULL_NAME_UPPER_TOKEN(node_id))), \
18+
(BSP_CLOCKS_CLOCK_DISABLED))
19+
20+
#define RA_CGC_CLK_DIV(clk, prop, default_value) \
21+
UTIL_CAT(RA_CGC_DIV_, DT_NODE_FULL_NAME_UPPER_TOKEN(clk)) \
22+
(RA_CGC_PROP_HAS_STATUS_OKAY_OR(clk, prop, default_value))
23+
24+
#define RA_CGC_DIV_BCLK(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)
25+
#define RA_CGC_DIV_CANFDCLK(n) UTIL_CAT(BSP_CLOCKS_CANFD_CLOCK_DIV_, n)
26+
#define RA_CGC_DIV_CECCLK(n) UTIL_CAT(BSP_CLOCKS_CEC_CLOCK_DIV_, n)
27+
#define RA_CGC_DIV_CLKOUT(n) UTIL_CAT(BSP_CLOCKS_CLKOUT_DIV_, n)
28+
#define RA_CGC_DIV_CPUCLK(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)
29+
#define RA_CGC_DIV_FCLK(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)
30+
#define RA_CGC_DIV_I3CCLK(n) UTIL_CAT(BSP_CLOCKS_I3C_CLOCK_DIV_, n)
31+
#define RA_CGC_DIV_ICLK(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)
32+
#define RA_CGC_DIV_LCDCLK(n) UTIL_CAT(BSP_CLOCKS_LCD_CLOCK_DIV_, n)
33+
#define RA_CGC_DIV_OCTASPICLK(n) UTIL_CAT(BSP_CLOCKS_OCTA_CLOCK_DIV_, n)
34+
#define RA_CGC_DIV_PCLKA(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)
35+
#define RA_CGC_DIV_PCLKB(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)
36+
#define RA_CGC_DIV_PCLKC(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)
37+
#define RA_CGC_DIV_PCLKD(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)
38+
#define RA_CGC_DIV_PCLKE(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)
39+
#define RA_CGC_DIV_PLL(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)
40+
#define RA_CGC_DIV_PLL2(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)
41+
#define RA_CGC_DIV_SCICLK(n) UTIL_CAT(BSP_CLOCKS_SCI_CLOCK_DIV_, n)
42+
#define RA_CGC_DIV_SPICLK(n) UTIL_CAT(BSP_CLOCKS_SPI_CLOCK_DIV_, n)
43+
#define RA_CGC_DIV_U60CLK(n) UTIL_CAT(BSP_CLOCKS_USB60_CLOCK_DIV_, n)
44+
#define RA_CGC_DIV_UCLK(n) UTIL_CAT(BSP_CLOCKS_USB_CLOCK_DIV_, n)
45+
46+
#define BSP_CLOCKS_SOURCE_PLL BSP_CLOCKS_SOURCE_CLOCK_PLL
47+
#define BSP_CLOCKS_SOURCE_PLL2 BSP_CLOCKS_SOURCE_CLOCK_PLL
48+
49+
#define BSP_CLOCKS_CLKOUT_DIV_1 (0)
50+
#define BSP_CLOCKS_CLKOUT_DIV_2 (1)
51+
#define BSP_CLOCKS_CLKOUT_DIV_4 (2)
52+
#define BSP_CLOCKS_CLKOUT_DIV_8 (3)
53+
#define BSP_CLOCKS_CLKOUT_DIV_16 (4)
54+
#define BSP_CLOCKS_CLKOUT_DIV_32 (5)
55+
#define BSP_CLOCKS_CLKOUT_DIV_64 (6)
56+
#define BSP_CLOCKS_CLKOUT_DIV_128 (7)
57+
1258
struct clock_control_ra_pclk_cfg {
1359
uint32_t clk_src;
1460
uint32_t clk_div;

‎include/zephyr/dt-bindings/clock/ra_clock.h‎

Lines changed: 0 additions & 130 deletions
Original file line numberDiff line numberDiff line change
@@ -7,136 +7,6 @@
77
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_
88
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_
99

10-
#define RA_PLL_SOURCE_HOCO 0
11-
#define RA_PLL_SOURCE_MOCO 1
12-
#define RA_PLL_SOURCE_LOCO 2
13-
#define RA_PLL_SOURCE_MAIN_OSC 3
14-
#define RA_PLL_SOURCE_SUBCLOCK 4
15-
#define RA_PLL_SOURCE_DISABLE 0xff
16-
17-
#define RA_CLOCK_SOURCE_HOCO 0
18-
#define RA_CLOCK_SOURCE_MOCO 1
19-
#define RA_CLOCK_SOURCE_LOCO 2
20-
#define RA_CLOCK_SOURCE_MAIN_OSC 3
21-
#define RA_CLOCK_SOURCE_SUBCLOCK 4
22-
#define RA_CLOCK_SOURCE_PLL 5
23-
#define RA_CLOCK_SOURCE_PLL1P RA_CLOCK_SOURCE_PLL
24-
#define RA_CLOCK_SOURCE_PLL2 6
25-
#define RA_CLOCK_SOURCE_PLL2P RA_CLOCK_SOURCE_PLL2
26-
#define RA_CLOCK_SOURCE_PLL1Q 7
27-
#define RA_CLOCK_SOURCE_PLL1R 8
28-
#define RA_CLOCK_SOURCE_PLL2Q 9
29-
#define RA_CLOCK_SOURCE_PLL2R 10
30-
#define RA_CLOCK_SOURCE_DISABLE 0xff
31-
32-
#define RA_SYS_CLOCK_DIV_1 0
33-
#define RA_SYS_CLOCK_DIV_2 1
34-
#define RA_SYS_CLOCK_DIV_4 2
35-
#define RA_SYS_CLOCK_DIV_8 3
36-
#define RA_SYS_CLOCK_DIV_16 4
37-
#define RA_SYS_CLOCK_DIV_32 5
38-
#define RA_SYS_CLOCK_DIV_64 6
39-
#define RA_SYS_CLOCK_DIV_128 7 /* available for CLKOUT only */
40-
#define RA_SYS_CLOCK_DIV_3 8
41-
#define RA_SYS_CLOCK_DIV_6 9
42-
#define RA_SYS_CLOCK_DIV_12 10
43-
44-
/* PLL divider options. */
45-
#define RA_PLL_DIV_1 0
46-
#define RA_PLL_DIV_2 1
47-
#define RA_PLL_DIV_3 2
48-
#define RA_PLL_DIV_4 3
49-
#define RA_PLL_DIV_5 4
50-
#define RA_PLL_DIV_6 5
51-
#define RA_PLL_DIV_8 7
52-
#define RA_PLL_DIV_9 8
53-
#define RA_PLL_DIV_16 15
54-
55-
/* USB clock divider options. */
56-
#define RA_USB_CLOCK_DIV_1 0
57-
#define RA_USB_CLOCK_DIV_2 1
58-
#define RA_USB_CLOCK_DIV_3 2
59-
#define RA_USB_CLOCK_DIV_4 3
60-
#define RA_USB_CLOCK_DIV_5 4
61-
#define RA_USB_CLOCK_DIV_6 5
62-
#define RA_USB_CLOCK_DIV_8 7
63-
64-
/* USB60 clock divider options. */
65-
#define RA_USB60_CLOCK_DIV_1 0
66-
#define RA_USB60_CLOCK_DIV_2 1
67-
#define RA_USB60_CLOCK_DIV_3 5
68-
#define RA_USB60_CLOCK_DIV_4 2
69-
#define RA_USB60_CLOCK_DIV_5 6
70-
#define RA_USB60_CLOCK_DIV_6 3
71-
#define RA_USB60_CLOCK_DIV_8 4
72-
73-
/* OCTA clock divider options. */
74-
#define RA_OCTA_CLOCK_DIV_1 0
75-
#define RA_OCTA_CLOCK_DIV_2 1
76-
#define RA_OCTA_CLOCK_DIV_4 2
77-
#define RA_OCTA_CLOCK_DIV_6 3
78-
#define RA_OCTA_CLOCK_DIV_8 4
79-
80-
/* CANFD clock divider options. */
81-
#define RA_CANFD_CLOCK_DIV_1 0
82-
#define RA_CANFD_CLOCK_DIV_2 1
83-
#define RA_CANFD_CLOCK_DIV_3 5
84-
#define RA_CANFD_CLOCK_DIV_4 2
85-
#define RA_CANFD_CLOCK_DIV_5 6
86-
#define RA_CANFD_CLOCK_DIV_6 3
87-
#define RA_CANFD_CLOCK_DIV_8 4
88-
89-
/* SCI clock divider options. */
90-
#define RA_SCI_CLOCK_DIV_1 0
91-
#define RA_SCI_CLOCK_DIV_2 1
92-
#define RA_SCI_CLOCK_DIV_3 5
93-
#define RA_SCI_CLOCK_DIV_4 2
94-
#define RA_SCI_CLOCK_DIV_5 6
95-
#define RA_SCI_CLOCK_DIV_6 3
96-
#define RA_SCI_CLOCK_DIV_8 4
97-
98-
/* SPI clock divider options. */
99-
#define RA_SPI_CLOCK_DIV_1 0
100-
#define RA_SPI_CLOCK_DIV_2 1
101-
#define RA_SPI_CLOCK_DIV_3 5
102-
#define RA_SPI_CLOCK_DIV_4 2
103-
#define RA_SPI_CLOCK_DIV_5 6
104-
#define RA_SPI_CLOCK_DIV_6 3
105-
#define RA_SPI_CLOCK_DIV_8 4
106-
107-
/* CEC clock divider options. */
108-
#define RA_CEC_CLOCK_DIV_1 0
109-
#define RA_CEC_CLOCK_DIV_2 1
110-
111-
/* I3C clock divider options. */
112-
#define RA_I3C_CLOCK_DIV_1 0
113-
#define RA_I3C_CLOCK_DIV_2 1
114-
#define RA_I3C_CLOCK_DIV_3 5
115-
#define RA_I3C_CLOCK_DIV_4 2
116-
#define RA_I3C_CLOCK_DIV_5 6
117-
#define RA_I3C_CLOCK_DIV_6 3
118-
#define RA_I3C_CLOCK_DIV_8 4
119-
120-
/* LCD clock divider options. */
121-
#define RA_LCD_CLOCK_DIV_1 0
122-
#define RA_LCD_CLOCK_DIV_2 1
123-
#define RA_LCD_CLOCK_DIV_3 5
124-
#define RA_LCD_CLOCK_DIV_4 2
125-
#define RA_LCD_CLOCK_DIV_5 6
126-
#define RA_LCD_CLOCK_DIV_6 3
127-
#define RA_LCD_CLOCK_DIV_8 4
128-
129-
/* SDADC clock divider options. */
130-
#define RA_SDADC_CLOCK_DIV_1 0
131-
#define RA_SDADC_CLOCK_DIV_2 1
132-
#define RA_SDADC_CLOCK_DIV_3 2
133-
#define RA_SDADC_CLOCK_DIV_4 3
134-
#define RA_SDADC_CLOCK_DIV_5 4
135-
#define RA_SDADC_CLOCK_DIV_6 5
136-
#define RA_SDADC_CLOCK_DIV_8 6
137-
#define RA_SDADC_CLOCK_DIV_12 7
138-
#define RA_SDADC_CLOCK_DIV_16 8
139-
14010
#define MSTPA 0
14111
#define MSTPB 1
14212
#define MSTPC 2

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