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Jacky Leekartben
Jacky Lee
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kartben
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soc: Add Egis et171
This is a SOC based on AE350. In addition to the core, some modifications have been made to the peripheral functions, including the integration of built-in USB. Signed-off-by: Jacky Lee <[email protected]>
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‎dts/bindings/vendor-prefixes.txt‎

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@@ -201,6 +201,7 @@ eckelmann Eckelmann AG
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edt Emerging Display Technologies
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eeti eGalax_eMPIA Technology Inc
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efinix Efinix Inc
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egis Egis Technology Inc
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einfochips Einfochips
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elan Elan Microelectronic Corp.
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electronut Electronut Labs

‎dts/riscv/egis/egis_et171.dtsi‎

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/*
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* Copyright (c) 2025 Egis Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <mem.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "andestech,andescore-v5", "riscv";
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device_type = "cpu";
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reg = <0>;
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riscv,isa = "rv32imafc_zicsr_zifencei";
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mmu-type = "riscv,sv32";
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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};
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sram: memory@0 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x00000000 DT_SIZE_K(384)>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "egis,et171";
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ranges;
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plic0: interrupt-controller@e4000000 {
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compatible = "sifive,plic-1.0.0", "andestech,nceplic100";
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#address-cells = <1>;
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe4000000 0x02000000>;
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riscv,max-priority = <255>;
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riscv,ndev = <1023>;
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interrupts-extended = <&cpu0_intc 11>;
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};
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plic_sw: interrupt-controller@e6400000 {
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compatible = "sifive,plic-1.0.0", "andestech,nceplic100";
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#address-cells = <1>;
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe6400000 0x00400000>;
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riscv,max-priority = <255>;
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riscv,ndev = <1023>;
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interrupts-extended = <&cpu0_intc 3>;
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};
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mtimer: timer@e6000000 {
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compatible = "riscv,machine-timer";
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reg-names = "mtime", "mtimecmp";
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reg = <0xe6000000 0x8 0xe6000008 0x8>;
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interrupts-extended = <&cpu0_intc 7>;
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};
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syscon: syscon@f0100000 {
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compatible = "syscon", "egis,et171-aosmu";
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reg = <0xf0100000 0x1000>;
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status = "disabled";
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};
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uart0: serial@f0200020 {
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compatible = "ns16550";
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reg = <0xf0200020 0x1000>;
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reg-shift = <2>;
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interrupts = <20 1>;
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interrupt-parent = <&plic0>;
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status = "disabled";
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};
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pit0: pit@f0400000 {
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compatible = "andestech,atcpit100";
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reg = <0xf0400000 0x1000>;
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interrupts = <22 1>;
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interrupt-parent = <&plic0>;
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clock-frequency = <60000000>;
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prescaler = <600>;
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status = "disabled";
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};
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rtc0: rtc@f0600000 {
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compatible = "andestech,atcrtc100";
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reg = <0xf0600000 0x1000>;
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interrupts = <31 1>;
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interrupt-parent = <&plic0>;
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wakeup-source;
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status = "disabled";
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};
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gpio0: gpio@f0700000 {
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compatible = "andestech,atcgpio100";
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reg = <0xf0700000 0x1000>;
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interrupts = <21 1>;
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interrupt-parent = <&plic0>;
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gpio-controller;
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ngpios = <17>;
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#gpio-cells = <2>;
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status = "disabled";
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};
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i2c0: i2c@f0a00000 {
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compatible = "andestech,atciic100";
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reg = <0xf0a00000 0x1000>;
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interrupts = <19 1>;
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interrupt-parent = <&plic0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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dma0: dma@f0c00000 {
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compatible = "andestech,atcdmacx00";
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reg = <0xf0c00000 0x1000>;
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interrupts = <16 1>;
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interrupt-parent = <&plic0>;
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dma-channels = <8>;
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dma-requests = <16>;
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chain-transfer = <1>;
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#dma-cells = <3>;
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status = "disabled";
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};
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wdt: wdt@f0500000 {
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compatible = "andestech,atcwdt200";
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reg = <0xf0500000 0x1000>;
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interrupts = <20 1>;
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interrupt-parent = <&plic0>;
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status = "disabled";
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};
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};
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};

‎soc/egis/CMakeLists.txt‎

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# Copyright (c) 2025 Egis Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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add_subdirectory(${SOC_NAME})

‎soc/egis/Kconfig‎

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# Copyright (c) 2025 Egis Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_EGIS_ET171
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rsource "*/Kconfig"
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endif # SOC_EGIS_ET171

‎soc/egis/Kconfig.defconfig‎

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# Copyright (c) 2025 Egis Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_EGIS_ET171
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rsource "*/Kconfig.defconfig"
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endif # SOC_EGIS_ET171

‎soc/egis/Kconfig.soc‎

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# Copyright (c) 2025 Egis Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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rsource "*/Kconfig.soc"

‎soc/egis/et171/CMakeLists.txt‎

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# SPDX-License-Identifier: Apache-2.0
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zephyr_include_directories(.)
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zephyr_sources(
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soc.c
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start.S
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)
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zephyr_linker_sources(ROM_START SORT_KEY 0x0 common_linker/init.ld)
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zephyr_linker_sources_ifdef(CONFIG_XIP RAM_SECTIONS SORT_KEY 0x0 common_linker/ram_start_nonzero.ld)
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set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

‎soc/egis/et171/Kconfig‎

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# Copyright (c) 2025 Egis Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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config SOC_EGIS_ET171
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imply XIP
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select RISCV
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select RISCV_PRIVILEGED
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select RISCV_HAS_PLIC
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select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
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select RISCV_ISA_RV32I
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select RISCV_ISA_EXT_M
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_C
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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select ATOMIC_OPERATIONS_BUILTIN
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select INCLUDE_RESET_VECTOR
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select CPU_HAS_FPU
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select CPU_HAS_DCACHE
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select CPU_HAS_ICACHE
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select RISCV_PMP
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select HAS_FLASH_LOAD_OFFSET
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select SOC_EARLY_INIT_HOOK
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config SOC_EGIS_ET171_FIRMWARE_VERSION
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hex "Firmware version"
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default 0xAAAAAAAA
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help
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Firmware version info of bin header

‎soc/egis/et171/Kconfig.defconfig‎

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# Copyright (c) 2025 Egis Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_EGIS_ET171
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rsource "Kconfig.defconfig.et171"
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,/clocks/clk_mtimer,clock-frequency)
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config KERNEL_ENTRY
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default "entry"
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config RISCV_GENERIC_TOOLCHAIN
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default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "zephyr"
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config RISCV_SOC_INTERRUPT_INIT
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default y
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config PMP_NO_NA4
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default y
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config PMP_GRANULARITY
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default 8
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config 2ND_LVL_ISR_TBL_OFFSET
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default 12
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config 2ND_LVL_INTR_00_OFFSET
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default 11
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config 2ND_LVL_INTR_01_OFFSET
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default 3
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config MAX_IRQ_PER_AGGREGATOR
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default 52
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config NUM_2ND_LEVEL_AGGREGATORS
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default 2
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config NUM_IRQS
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default 116
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choice CACHE_TYPE
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default EXTERNAL_CACHE
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endchoice
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endif # SOC_EGIS_ET171

‎soc/egis/et171/Kconfig.defconfig.et171‎

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# Copyright (c) 2025 Egis Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_EGIS_ET171
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config SYS_CLOCK_TICKS_PER_SEC
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default 100 if (!ICACHE || XIP)
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config MAIN_STACK_SIZE
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default 2048
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config IDLE_STACK_SIZE
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default 1536
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config LINKER_USE_RELAX
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default n if XIP
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endif # SOC_EGIS_ET171

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