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21 | 21 | #define ADI_MAX32_I2C_INT_FL0_MASK 0x00FFFFFF |
22 | 22 | #define ADI_MAX32_I2C_INT_FL1_MASK 0x7 |
23 | 23 |
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24 | | -#define ADI_MAX32_I2C_STATUS_MASTER_BUSY BIT(5) |
25 | | - |
26 | 24 | #define I2C_RECOVER_MAX_RETRIES 3 |
27 | 25 |
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28 | 26 | #ifdef CONFIG_I2C_MAX32_DMA |
@@ -540,8 +538,7 @@ static int i2c_max32_transfer(const struct device *dev, struct i2c_msg *msgs, ui |
540 | 538 | /* Wait for busy flag to be cleared for clock stetching |
541 | 539 | * use-cases |
542 | 540 | */ |
543 | | - while (i2c->status & ADI_MAX32_I2C_STATUS_MASTER_BUSY) { |
544 | | - } |
| 541 | + Wrap_MXC_I2C_WaitForBusyClear(i2c); |
545 | 542 | MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, |
546 | 543 | ADI_MAX32_I2C_INT_FL1_MASK); |
547 | 544 | } |
@@ -650,7 +647,7 @@ static void i2c_max32_isr_target(const struct device *dev, mxc_i2c_regs_t *i2c) |
650 | 647 | uint32_t int_en0; |
651 | 648 | uint32_t int_en1; |
652 | 649 |
|
653 | | - ctrl = i2c->ctrl; |
| 650 | + Wrap_MXC_I2C_GetCtrl(i2c, &ctrl); |
654 | 651 | Wrap_MXC_I2C_GetIntEn(i2c, &int_en0, &int_en1); |
655 | 652 | MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1); |
656 | 653 | MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK); |
@@ -710,7 +707,7 @@ static void i2c_max32_isr_target(const struct device *dev, mxc_i2c_regs_t *i2c) |
710 | 707 | if (int_en0 & ADI_MAX32_I2C_INT_EN0_ADDR_MATCH) { |
711 | 708 | if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ADDR_MATCH) { |
712 | 709 | /* Address match occurred, prepare for transaction */ |
713 | | - if (i2c->ctrl & MXC_F_I2C_CTRL_READ) { |
| 710 | + if (Wrap_MXC_I2C_GetReadWriteBitStatus(i2c)) { |
714 | 711 | /* Read request received from the master */ |
715 | 712 | i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_MASTER_RD); |
716 | 713 | int_en0 = ADI_MAX32_I2C_INT_EN0_TX_THD | |
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