soc: arm: reneas: Add r8a779f0 support

r8a779f0 SoC is part of the Renesas R-Car Gen4 SoC series.

This SoC has a dual core lockstep Cortex-R52 CPU.

L1 cache and branch prediction are enabled for Renesas RCar Gen4 SoCs.

Signed-off-by: Aymeric Aillet <[email protected]>

Author: aaillet

soc/arm/renesas_rcar/gen4/CMakeLists.txt

@@ -1,4 +1,7 @@
 # Copyright (c) 2023 IoT.bzh
 # SPDX-License-Identifier: Apache-2.0
 
-zephyr_library_sources_ifdef(CONFIG_SOC_R8A779F0 pfc_r8a779f0.c)
+zephyr_sources(
+  soc.c
+)
+zephyr_library_sources_ifdef(CONFIG_SOC_R8A779F0 pfc_r8a779f0.c)

soc/arm/renesas_rcar/gen4/Kconfig.defconfig.r8a779f0

@@ -0,0 +1,15 @@
+# Copyright (c) 2023 IoT.bzh
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_R8A779F0
+
+config SOC
+	default "r8a779f0"
+
+config NUM_IRQS
+	default 1216 #960 SPI + 256 LPI
+
+config PINCTRL
+	default y
+
+endif # SOC_R8A779F0

soc/arm/renesas_rcar/gen4/Kconfig.defconfig.series

@@ -0,0 +1,13 @@
+# Renesas R-Car Gen4 SoC line
+
+# Copyright (c) 2023 IoT.bzh
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RCAR_GEN4
+
+source "soc/arm/renesas_rcar/gen4/Kconfig.defconfig.r8a779*"
+
+config SOC_SERIES
+	default "gen4"
+
+endif # SOC_SERIES_RCAR_GEN4

soc/arm/renesas_rcar/gen4/Kconfig.series

@@ -0,0 +1,15 @@
+# Copyright (c) 2023 IoT.bzh
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RCAR_GEN4
+	bool "Renesas R-Car Gen4 Cortex R52"
+	select ARM
+	select CPU_CORTEX_R52
+	select PLATFORM_SPECIFIC_INIT
+	select GIC_V3
+	select GIC_SINGLE_SECURITY_STATE
+	select SOC_FAMILY_RCAR
+	select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL
+	select ARM_ARCH_TIMER
+	help
+	  Enable support for Renesas R-Car Gen4 SoC series

soc/arm/renesas_rcar/gen4/Kconfig.soc

@@ -0,0 +1,11 @@
+# Copyright (c) 2023 IoT.bzh
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+	prompt "Renesas RCar SoC Selection"
+	depends on SOC_SERIES_RCAR_GEN4
+
+config SOC_R8A779F0
+	bool "r8a779f0"
+
+endchoice

soc/arm/renesas_rcar/gen4/linker.ld

@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2023 IoT.bzh
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/arm/aarch32/cortex_a_r/scripts/linker.ld>

soc/arm/renesas_rcar/gen4/soc.c

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2023 IoT.bzh
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+
+/**
+ *
+ * @brief Perform basic hardware initialization
+ *
+ * @return 0
+ */
+
+static int soc_init(const struct device *arg)
+{
+	ARG_UNUSED(arg);
+
+	/* Install default handler that simply resets the CPU
+	 * if configured in the kernel, NOP otherwise
+	 */
+	NMI_INIT();
+	return 0;
+}
+
+void z_arm_platform_init(void)
+{
+	L1C_DisableCaches();
+	L1C_DisableBTAC();
+
+	/* Invalidate instruction cache and flush branch target cache */
+	__set_ICIALLU(0);
+	__DSB();
+	__ISB();
+
+	L1C_EnableCaches();
+	L1C_EnableBTAC();
+}
+
+SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

soc/arm/renesas_rcar/gen4/soc.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2023 IoT.bzh
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#ifndef _SOC__H_
+#define _SOC__H_
+
+/* Define CMSIS configurations */
+#define __CR_REV      1U
+
+/* Do not let CMSIS to handle GIC and Timer */
+#define __GIC_PRESENT 0
+#define __TIM_PRESENT 0
+
+#endif /* _SOC__H_ */