tests: drivers: adc_dma: add nucleo_h743zi

Adds nucleo_h732zi ADC DMA unit tests with multiple channels.

The STM32 ADC DMA driver requires the buffers to be placed
in a non-cacheable memory region as defined by the DMA.
Therefore this adds configurability to the test to change
the region the buffer is placed in.

Signed-off-by: Hein Wessels <[email protected]>

Author: heinwessels

tests/drivers/adc/adc_dma/boards/nucleo_h743zi.conf

@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2023 Nobleo Technology
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_ADC_STM32_DMA=y
+CONFIG_ADC_ASYNC=y

tests/drivers/adc/adc_dma/boards/nucleo_h743zi.overlay

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2023 Nobleo Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+&adc1 {
+	dmas = < &dmamux1 0 9 (STM32_DMA_PERIPH_TO_MEMORY |
+		STM32_DMA_MEM_INC |  STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS) >;
+	dma-names = "dmamux";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+};
+
+/* ADC driver expects a buffer in a non-cachable memory region */
+&sram4 {
+	zephyr,memory-region-mpu = "RAM_NOCACHE";
+};
+
+&dma1 {
+	status = "okay";
+};
+
+test_dma: &dmamux1 {
+	status = "okay";
+};

tests/drivers/adc/adc_dma/src/test_adc.c

@@ -35,6 +35,33 @@
 #define COUNTER_NODE_NAME pit0
 #define HW_TRIGGER_INTERVAL (2U)
 
+#elif defined(CONFIG_BOARD_NUCLEO_H743ZI)
+
+#define ADC_DEVICE_NODE DT_INST(0, st_stm32_adc)
+#define ADC_RESOLUTION 12
+#define ADC_GAIN ADC_GAIN_1
+#define ADC_REFERENCE ADC_REF_INTERNAL
+#define ADC_ACQUISITION_TIME ADC_ACQ_TIME_DEFAULT
+#define ADC_1ST_CHANNEL_ID 1
+#define ADC_2ND_CHANNEL_ID 7
+#define ALIGNMENT 32
+#define BUFFER_MEM_REGION __attribute__((__section__(".sram4")))
+
+#endif
+
+/* Invalid value that is not supposed to be written by the driver. It is used
+ * to mark the sample buffer entries as empty. If needed, it can be overridden
+ * for a particular board by providing a specific definition above.
+ */
+#if !defined(INVALID_ADC_VALUE)
+#define INVALID_ADC_VALUE SHRT_MIN
+#endif
+
+/* Memory region where buffers will be placed. By default placed in ZTEST_BMEM
+ * but can be overwritten for a particular board.
+ */
+#if !defined(BUFFER_MEM_REGION)
+#define BUFFER_MEM_REGION EMPTY
 #endif
 
 /* for DMA HW trigger interval need large than HW trigger interval*/
@@ -45,8 +72,8 @@
 #define ALIGNMENT DMA_BUF_ADDR_ALIGNMENT(DT_NODELABEL(test_dma))
 #endif
 
-static __aligned(ALIGNMENT) int16_t m_sample_buffer[BUFFER_SIZE];
-static __aligned(ALIGNMENT) int16_t m_sample_buffer2[2][BUFFER_SIZE];
+static BUFFER_MEM_REGION __aligned(ALIGNMENT) int16_t m_sample_buffer[BUFFER_SIZE];
+static BUFFER_MEM_REGION __aligned(ALIGNMENT) int16_t m_sample_buffer2[2][BUFFER_SIZE];
 static int current_buf_inx;
 
 #if defined(CONFIG_ADC_ASYNC)