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boards: coredevices: add pebble 2 duo
Add board for Pebble 2 Duo. Most peripherals are supported, however, some upstream changes are needed to take full benefit of some. Signed-off-by: Gerard Marull-Paretas <[email protected]>
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‎boards/coredevices/p2d/Kconfig.p2d‎

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# Copyright (c) 2025 Core Devices LLC
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_P2D
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select SOC_NRF52840_QIAA

‎boards/coredevices/p2d/board.cmake‎

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# Copyright (c) 2025 Core Devices LLC
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# SPDX-License-Identifier: Apache-2.0
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board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000")
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board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000")
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include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake)

‎boards/coredevices/p2d/board.yml‎

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# Copyright (c) 2025 Core Devices LLC
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# SPDX-License-Identifier: Apache-2.0
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boards:
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- name: p2d
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full_name: Pebble 2 Duo
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vendor: coredevices
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socs:
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- name: nrf52840

‎boards/coredevices/p2d/doc/img/p2d.webp‎

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‎boards/coredevices/p2d/doc/index.rst‎

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.. zephyr:board:: p2d
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Overview
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********
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Pebble 2 Duo is a smart watch based on the nRF52840 series chip SoC.
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More information about the watch can be found at the `RePebble website`_.
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Hardware
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********
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Pebble 2 Duo provides the following hardware components:
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- Nordic nRF52840
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- nPM1300 PMIC for power supply and battery charging
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- GD25LE255E 256 Mb QSPI NOR
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- Sharp LS013B7DH05 Memory-in-Pixel (MiP) monochrome display
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- PWM backlight control using TPS22916 driver
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- OPT3001 ambient light sensor
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- 4 physical buttons
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- LSM6DSOW IMU (accelerometer/gyroscope)
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- MMC5603NJ magnetometer
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- MSM261DDB020 PDM microphone
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- Speaker driven by DA7212 audio codec
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- LRA driven by TI DRV2604 haptic driver
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- Programming connector
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Supported Features
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==================
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.. zephyr:board-supported-hw::
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Programming and Debugging
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*************************
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.. zephyr:board-supported-runners::
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References
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**********
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.. target-notes::
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.. _RePebble website:
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https://repebble.com/

‎boards/coredevices/p2d/p2d-pinctrl.dtsi‎

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/*
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* Copyright (c) 2025 Core Devices LLC
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* SPDX-License-Identifier: Apache-2.0
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*/
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&pinctrl {
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i2c0_default: i2c0_default {
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group1 {
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psels = <NRF_PSEL(TWIM_SDA, 0, 15)>,
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<NRF_PSEL(TWIM_SCL, 0, 14)>;
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};
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};
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i2c0_sleep: i2c0_sleep {
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group1 {
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psels = <NRF_PSEL(TWIM_SDA, 0, 15)>,
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<NRF_PSEL(TWIM_SCL, 0, 14)>;
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low-power-enable;
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};
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};
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i2c1_default: i2c1_default {
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group1 {
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psels = <NRF_PSEL(TWIM_SDA, 0, 11)>,
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<NRF_PSEL(TWIM_SCL, 0, 25)>;
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};
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};
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i2c1_sleep: i2c1_sleep {
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group1 {
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psels = <NRF_PSEL(TWIM_SDA, 0, 11)>,
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<NRF_PSEL(TWIM_SCL, 0, 25)>;
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low-power-enable;
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};
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};
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i2s0_default: i2s0_default {
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group1 {
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psels = <NRF_PSEL(I2S_MCK, 1, 9)>,
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<NRF_PSEL(I2S_SCK_M, 0, 12)>,
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<NRF_PSEL(I2S_LRCK_M, 0, 7)>,
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<NRF_PSEL(I2S_SDOUT, 0, 13)>;
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};
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};
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i2s0_sleep: i2s0_sleep {
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group1 {
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psels = <NRF_PSEL(I2S_MCK, 1, 9)>,
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<NRF_PSEL(I2S_SCK_M, 0, 12)>,
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<NRF_PSEL(I2S_LRCK_M, 0, 7)>,
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<NRF_PSEL(I2S_SDOUT, 0, 13)>;
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low-power-enable;
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};
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};
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pdm0_default: pdm0_default {
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group1 {
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psels = <NRF_PSEL(PDM_CLK, 1, 0)>,
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<NRF_PSEL(PDM_DIN, 0, 24)>;
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};
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};
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pwm0_default: pwm0_default {
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group1 {
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psels = <NRF_PSEL(PWM_OUT0, 0, 26)>;
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};
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};
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pwm0_sleep: pwm0_sleep {
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group1 {
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psels = <NRF_PSEL(PWM_OUT0, 0, 26)>;
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low-power-enable;
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};
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};
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qspi_default: qspi_default {
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group1 {
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psels = <NRF_PSEL(QSPI_SCK, 0, 19)>,
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<NRF_PSEL(QSPI_IO0, 0, 20)>,
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<NRF_PSEL(QSPI_IO1, 0, 21)>,
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<NRF_PSEL(QSPI_IO2, 0, 22)>,
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<NRF_PSEL(QSPI_IO3, 0, 23)>,
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<NRF_PSEL(QSPI_CSN, 0, 17)>;
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nordic,drive-mode = <NRF_DRIVE_H0H1>;
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};
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};
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qspi_sleep: qspi_sleep {
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group1 {
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psels = <NRF_PSEL(QSPI_SCK, 0, 19)>,
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<NRF_PSEL(QSPI_IO0, 0, 20)>,
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<NRF_PSEL(QSPI_IO1, 0, 21)>,
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<NRF_PSEL(QSPI_IO2, 0, 22)>,
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<NRF_PSEL(QSPI_IO3, 0, 23)>;
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low-power-enable;
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};
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group2 {
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psels = <NRF_PSEL(QSPI_CSN, 0, 17)>;
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low-power-enable;
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bias-pull-up;
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};
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};
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spi3_default: spi3_default {
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group1 {
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psels = <NRF_PSEL(SPIM_SCK, 0, 6)>,
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<NRF_PSEL(SPIM_MOSI, 0, 8)>;
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};
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};
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spi3_sleep: spi3_sleep {
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group1 {
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psels = <NRF_PSEL(SPIM_SCK, 0, 6)>,
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<NRF_PSEL(SPIM_MOSI, 0, 8)>;
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low-power-enable;
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};
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};
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uart0_default: uart0_default {
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group1 {
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psels = <NRF_PSEL(UART_TX, 0, 27)>;
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};
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group2 {
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psels = <NRF_PSEL(UART_RX, 0, 5)>;
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bias-pull-up;
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};
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};
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uart0_sleep: uart0_sleep {
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group1 {
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psels = <NRF_PSEL(UART_TX, 0, 27)>,
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<NRF_PSEL(UART_RX, 0, 5)>;
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low-power-enable;
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};
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};
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};

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