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drivers: system timer: Initial support for RZ/G3S
Add System Timer driver support for Renesas RZ/G3S Signed-off-by: Nhut Nguyen <[email protected]> Signed-off-by: Hoang Nguyen <[email protected]>
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‎drivers/timer/CMakeLists.txt

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@@ -47,5 +47,6 @@ zephyr_library_sources_ifdef(CONFIG_XTENSA_TIMER xtensa_sys_timer.c)
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zephyr_library_sources_ifdef(CONFIG_SMARTBOND_TIMER smartbond_timer.c)
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zephyr_library_sources_ifdef(CONFIG_MTK_ADSP_TIMER mtk_adsp_timer.c)
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zephyr_library_sources_ifdef(CONFIG_SY1XX_SYS_TIMER sy1xx_sys_timer.c)
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zephyr_library_sources_ifdef(CONFIG_RZ_OS_TIMER renesas_rz_gtm_timer.c)
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zephyr_library_sources_ifdef(CONFIG_RZA2M_OS_TIMER renesas_rza2m_os_timer.c)
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zephyr_library_sources_ifdef(CONFIG_INFINEON_CAT1_LP_TIMER ifx_cat1_lp_timer.c)

‎drivers/timer/Kconfig

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@@ -105,6 +105,7 @@ source "drivers/timer/Kconfig.xtensa"
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source "drivers/timer/Kconfig.mtk_adsp"
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source "drivers/timer/Kconfig.sy1xx_sys_timer"
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source "drivers/timer/Kconfig.renesas_ra_ulpt"
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source "drivers/timer/Kconfig.renesas_rz"
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source "drivers/timer/Kconfig.renesas_rza2m"
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source "drivers/timer/Kconfig.ifx_cat1_lp"
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‎drivers/timer/Kconfig.renesas_rz

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config RZ_OS_TIMER
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bool "Renesas RZ OS timer"
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default y
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depends on DT_HAS_RENESAS_RZ_GTM_OS_TIMER_ENABLED
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select TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
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select SYSTEM_TIMER_HAS_DISABLE_SUPPORT
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select TICKLESS_CAPABLE
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select USE_RZ_FSP_GTM
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help
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This module implements a kernel device driver for the Renesas RZ
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platform provides the standard "system clock driver" interfaces.

‎drivers/timer/renesas_rz_gtm_timer.c

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/device.h>
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#include <zephyr/spinlock.h>
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#include <zephyr/drivers/timer/system_timer.h>
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#include <zephyr/irq.h>
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#include <zephyr/sys_clock.h>
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#include <zephyr/logging/log.h>
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#include <instances/rzg/r_gtm.h>
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LOG_MODULE_REGISTER(renesas_rz_gtm_timer);
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#define DT_DRV_COMPAT renesas_rz_gtm_os_timer
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#define TIMER_NODE DT_INST_PARENT(0)
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#define cycle_diff_t uint32_t
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#define CYCLE_DIFF_MAX (~(cycle_diff_t)0)
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/*
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* We have two constraints on the maximum number of cycles we can wait for.
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*
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* 1) sys_clock_announce() accepts at most INT32_MAX ticks.
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*
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* 2) The number of cycles between two reports must fit in a cycle_diff_t
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* variable before converting it to ticks.
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*
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* Then:
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*
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* 3) Pick the smallest between (1) and (2).
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*
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* 4) Take into account some room for the unavoidable IRQ servicing latency.
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* Let's use 3/4 of the max range.
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*
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* Finally let's add the LSB value to the result so to clear out a bunch of
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* consecutive set bits coming from the original max values to produce a
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* nicer literal for assembly generation.
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*/
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#define CYCLES_MAX_1 ((uint64_t)INT32_MAX * (uint64_t)CYC_PER_TICK)
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#define CYCLES_MAX_2 ((uint64_t)CYCLE_DIFF_MAX)
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#define CYCLES_MAX_3 MIN(CYCLES_MAX_1, CYCLES_MAX_2)
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#define CYCLES_MAX_4 (CYCLES_MAX_3 / 2 + CYCLES_MAX_3 / 4)
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#define CYCLES_MAX_5 (CYCLES_MAX_4 + LSB_GET(CYCLES_MAX_4))
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/* precompute CYCLES_MAX and CYC_PER_TICK at driver init to avoid runtime double divisions */
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static uint64_t cycles_max;
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static uint32_t cyc_per_tick;
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#define CYCLES_MAX cycles_max
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#define CYC_PER_TICK cyc_per_tick
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static void ostm_irq_handler(timer_callback_args_t *arg);
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void gtm_int_isr(void);
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const struct device *g_os_timer_dev = DEVICE_DT_INST_GET(0);
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extern unsigned int z_clock_hw_cycles_per_sec;
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struct rz_os_timer_config {
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timer_cfg_t *fsp_cfg;
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const timer_api_t *fsp_api;
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};
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struct rz_os_timer_data {
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timer_ctrl_t *fsp_ctrl;
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struct k_spinlock lock;
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uint32_t last_cycle;
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uint32_t last_tick;
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uint32_t last_elapsed;
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};
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static void ostm_irq_handler(timer_callback_args_t *arg)
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{
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ARG_UNUSED(arg);
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struct rz_os_timer_data *data = (struct rz_os_timer_data *)g_os_timer_dev->data;
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uint32_t delta_cycles = sys_clock_cycle_get_32() - data->last_cycle;
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uint32_t delta_ticks = delta_cycles / CYC_PER_TICK;
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data->last_cycle += delta_ticks * CYC_PER_TICK;
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data->last_tick += delta_ticks;
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data->last_elapsed = 0;
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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struct rz_os_timer_config *config =
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(struct rz_os_timer_config *)g_os_timer_dev->config;
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uint32_t next_cycle = data->last_cycle + CYC_PER_TICK;
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config->fsp_api->periodSet(data->fsp_ctrl, next_cycle);
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} else {
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irq_disable(DT_IRQN(TIMER_NODE));
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}
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/* Announce to the kernel */
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sys_clock_announce(delta_ticks);
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}
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void sys_clock_set_timeout(int32_t ticks, bool idle)
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{
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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return;
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}
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if (idle && ticks == K_TICKS_FOREVER) {
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return;
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}
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struct rz_os_timer_config *config = (struct rz_os_timer_config *)g_os_timer_dev->config;
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struct rz_os_timer_data *data = (struct rz_os_timer_data *)g_os_timer_dev->data;
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uint32_t next_cycle;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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if (ticks == K_TICKS_FOREVER) {
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next_cycle = data->last_cycle + CYCLES_MAX;
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} else {
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next_cycle = (data->last_tick + data->last_elapsed + ticks) * CYC_PER_TICK;
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if ((next_cycle - data->last_cycle) > CYCLES_MAX) {
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next_cycle = data->last_cycle + CYCLES_MAX;
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}
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}
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config->fsp_api->periodSet(data->fsp_ctrl, next_cycle);
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irq_enable(DT_IRQN(TIMER_NODE));
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k_spin_unlock(&data->lock, key);
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}
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uint32_t sys_clock_elapsed(void)
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{
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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return 0;
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}
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struct rz_os_timer_data *data = (struct rz_os_timer_data *)g_os_timer_dev->data;
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uint32_t delta_cycles = sys_clock_cycle_get_32() - data->last_cycle;
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uint32_t delta_ticks = delta_cycles / CYC_PER_TICK;
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data->last_elapsed = delta_ticks;
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return delta_ticks;
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}
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void sys_clock_disable(void)
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{
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struct rz_os_timer_config *config = (struct rz_os_timer_config *)g_os_timer_dev->config;
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struct rz_os_timer_data *data = (struct rz_os_timer_data *)g_os_timer_dev->data;
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config->fsp_api->close(data->fsp_ctrl);
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}
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uint32_t sys_clock_cycle_get_32(void)
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{
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struct rz_os_timer_config *config = (struct rz_os_timer_config *)g_os_timer_dev->config;
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struct rz_os_timer_data *data = (struct rz_os_timer_data *)g_os_timer_dev->data;
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timer_status_t timer_status;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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config->fsp_api->statusGet(data->fsp_ctrl, &timer_status);
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k_spin_unlock(&data->lock, key);
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return timer_status.counter;
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}
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static int sys_clock_driver_init(void)
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{
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fsp_err_t ret;
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struct rz_os_timer_config *config = (struct rz_os_timer_config *)g_os_timer_dev->config;
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struct rz_os_timer_data *data = (struct rz_os_timer_data *)g_os_timer_dev->data;
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IRQ_CONNECT(DT_IRQN(TIMER_NODE), DT_IRQ(TIMER_NODE, priority), gtm_int_isr,
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DEVICE_DT_INST_GET(0), 0);
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data->last_tick = 0;
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data->last_cycle = 0;
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z_clock_hw_cycles_per_sec = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_P0CLK);
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cyc_per_tick = sys_clock_hw_cycles_per_sec() / CONFIG_SYS_CLOCK_TICKS_PER_SEC;
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cycles_max = CYCLES_MAX_5;
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config->fsp_cfg->period_counts = CYC_PER_TICK;
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ret = config->fsp_api->open(data->fsp_ctrl, config->fsp_cfg);
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if (ret != FSP_SUCCESS) {
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LOG_ERR("timer initialize failed");
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return -EIO;
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}
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ret = config->fsp_api->start(data->fsp_ctrl);
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if (ret != FSP_SUCCESS) {
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LOG_ERR("timer start failed");
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return -EIO;
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}
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return 0;
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}
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#define OS_TIMER_RZG_GTM_INIT() \
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const gtm_extended_cfg_t g_timer0_extend = { \
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.generate_interrupt_when_starts = GTM_GIWS_TYPE_DISABLED, \
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.gtm_mode = GTM_TIMER_MODE_FREERUN, \
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}; \
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\
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static timer_cfg_t g_timer0_cfg = { \
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.mode = TIMER_MODE_PERIODIC, \
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.period_counts = 0, \
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.channel = DT_PROP(TIMER_NODE, channel), \
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.p_callback = ostm_irq_handler, \
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.p_context = DEVICE_DT_INST_GET(0), \
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.p_extend = &g_timer0_extend, \
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.cycle_end_ipl = DT_IRQ(TIMER_NODE, priority), \
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.cycle_end_irq = DT_IRQN(TIMER_NODE), \
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}; \
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\
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static gtm_instance_ctrl_t g_timer0_ctrl; \
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\
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static struct rz_os_timer_data g_rz_os_timer_data = { \
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.fsp_ctrl = (timer_ctrl_t *)&g_timer0_ctrl, \
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}; \
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\
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struct rz_os_timer_config g_rz_os_timer_config = { \
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.fsp_cfg = &g_timer0_cfg, \
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.fsp_api = &g_timer_on_gtm, \
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}; \
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\
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DEVICE_DT_INST_DEFINE(0, NULL, NULL, &g_rz_os_timer_data, &g_rz_os_timer_config, \
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PRE_KERNEL_2, CONFIG_SYSTEM_CLOCK_INIT_PRIORITY, NULL); \
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\
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SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2, CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
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OS_TIMER_RZG_GTM_INIT();

‎dts/bindings/timer/renesas,rz-gtm-os-timer.yaml

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: Renesas RZ OS timer
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compatible: "renesas,rz-gtm-os-timer"
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include: base.yaml

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