tests: drivers: adc: adc_api: update adc_api test

- add nucleo_c071rb overlay file to setup adc node

- The C0 serie has two HSI clock sources, HSI48 and HSI48USB.
To make it simpler and compatible with the existing clock driver,
HSI48 is renamed to HSI (node already present in the stm32c0.dtsi).
HSI48USB will correspond to HSI48.
With SYNC mode, we have an overrun on the ADC, so we configure it
in ASYNC mode.

- Update STM32 HSI macro according to changes

Signed-off-by: Fabrice DJIATSA <[email protected]>

Author: djiatsaf-st

boards/st/nucleo_c071rb/nucleo_c071rb.dts

@@ -72,6 +72,10 @@
 	status = "okay";
 };
 
+&clk_hsi {
+	status = "okay";
+};
+
 &rcc {
 	clocks = <&clk_hse>;
 	clock-frequency = <DT_FREQ_M(48)>;
@@ -138,7 +142,9 @@
 &adc1 {
 	pinctrl-0 = <&adc1_in0_pa0 &adc1_in1_pa1 &adc1_in4_pa4>;
 	pinctrl-names = "default";
-	st,adc-clock-source = "SYNC";
+	st,adc-clock-source = "ASYNC";
+	clocks = <&rcc STM32_CLOCK(APB1_2, 20U)>,
+		 <&rcc STM32_SRC_HSI ADC_SEL(2)>;
 	st,adc-prescaler = <4>;
 	status = "okay";
 	vref-mv = <3300>;

include/zephyr/dt-bindings/clock/stm32c0_clock.h

@@ -24,8 +24,8 @@
 /* defined in stm32_common_clocks.h */
 /** Fixed clocks  */
 /* Low speed clocks defined in stm32_common_clocks.h */
-#define STM32_SRC_HSI48		(STM32_SRC_LSI + 1)
-#define STM32_SRC_HSE		(STM32_SRC_HSI48 + 1)
+#define STM32_SRC_HSI		(STM32_SRC_LSI + 1)
+#define STM32_SRC_HSE		(STM32_SRC_HSI + 1)
 /** Peripheral bus clock */
 #define STM32_SRC_PCLK		(STM32_SRC_HSE + 1)
 

tests/drivers/adc/adc_api/boards/nucleo_c071rb.overlay

@@ -0,0 +1,38 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2025 STMicroelectronics
+ */
+
+/ {
+	zephyr,user {
+		/* adjust channel number according to pinmux in board.dts */
+		io-channels = <&adc1 0>, <&adc1 1>;
+	};
+};
+
+&adc1 {
+
+	dmas = <&dmamux1 0 5 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS |
+		STM32_DMA_PERIPH_16BITS)>;
+	dma-names = "dmamux";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_MAX>;
+		zephyr,resolution = <12>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_MAX>;
+		zephyr,resolution = <12>;
+	};
+};