soc: riscv: cleanup usage/definition of MCAUSE IRQ flag

gmarull · carlescufi · commit a364420b30f9 · 2024-01-15T09:58:03.000+01:00
The MCAUSE register has the "Interrupt" flag defined defined at XLEN-1
position (31 for 32-bit, 63 for 64-bit). This is not an SoC specific
option, and there's no need to expose it publicly.

Signed-off-by: Gerard Marull-Paretas &lt;gerard@teslabs.com&gt;
diff --git a/include/zephyr/arch/riscv/irq.h b/include/zephyr/arch/riscv/irq.h
@@ -32,6 +32,12 @@ extern "C" {
 /** Environment Call from M-mode */
 #define RISCV_EXC_ECALLM 11
 
+#ifdef CONFIG_64BIT
+#define RISCV_MCAUSE_IRQ_BIT          (1 << 63)
+#else
+#define RISCV_MCAUSE_IRQ_BIT          (1 << 31)
+#endif
+
 #ifndef _ASMLANGUAGE
 
 extern void arch_irq_enable(unsigned int irq);
diff --git a/soc/riscv/common/riscv-privileged/soc_common.h b/soc/riscv/common/riscv-privileged/soc_common.h
@@ -16,15 +16,6 @@
 #define RISCV_MACHINE_SOFT_IRQ       3  /* Machine Software Interrupt */
 #define RISCV_MACHINE_EXT_IRQ        11 /* Machine External Interrupt */
 
-/* SOC-specific MCAUSE bitfields */
-#ifdef CONFIG_64BIT
-/* Interrupt Mask */
-#define SOC_MCAUSE_IRQ_MASK          (1 << 63)
-#else
-/* Interrupt Mask */
-#define SOC_MCAUSE_IRQ_MASK          (1 << 31)
-#endif
-
 /* Exception code Mask */
 #define SOC_MCAUSE_EXP_MASK          CONFIG_RISCV_SOC_MCAUSE_EXCEPTION_MASK
 
diff --git a/soc/riscv/common/riscv-privileged/soc_irq.S b/soc/riscv/common/riscv-privileged/soc_irq.S
@@ -12,7 +12,7 @@
 #include <offsets.h>
 #include <zephyr/toolchain.h>
 #include <zephyr/linker/sections.h>
-#include <soc.h>
+#include <zephyr/arch/riscv/irq.h>
 
 /*
  * __soc_handle_irq is defined as .weak to allow re-implementation by
@@ -48,7 +48,7 @@ WTEXT(__soc_is_irq)
 SECTION_FUNC(exception.other, __soc_is_irq)
 	/* Read mcause and check if interrupt bit is set */
 	csrr t0, mcause
-	li t1, SOC_MCAUSE_IRQ_MASK
+	li t1, RISCV_MCAUSE_IRQ_BIT
 	and t0, t0, t1
 
 	/* If interrupt bit is not set, return with 0 */
diff --git a/soc/riscv/espressif_esp32/esp32c3/soc.h b/soc/riscv/espressif_esp32/esp32c3/soc.h
@@ -21,9 +21,6 @@
 #define RISCV_MACHINE_TIMER_IRQ 7 /* Machine Timer Interrupt */
 #define RISCV_MACHINE_EXT_IRQ 11 /* Machine External Interrupt */
 
-/* Interrupt Mask */
-#define SOC_MCAUSE_IRQ_MASK (1 << 31)
-
 /* Exception code Mask */
 #define SOC_MCAUSE_EXP_MASK 0x7FFFFFFF
 
diff --git a/soc/riscv/ite_ec/common/soc_common.h b/soc/riscv/ite_ec/common/soc_common.h
@@ -16,9 +16,6 @@
 
 /* SOC-specific MCAUSE bitfields */
 
-/* Interrupt Mask. 1 (interrupt) or 0 (exception) */
-#define SOC_MCAUSE_IRQ_MASK          BIT(31)
-
 /* Exception code Mask */
 #define SOC_MCAUSE_EXP_MASK          0x7FFFFFFF
 
