dts: renesas ra: RA4M3 series R7FA4M3AF3CFB.

Signed-off-by: Piotr Rak <[email protected]>

Author: piotrrak

dts/arm/renesas/ra/r7fa4m3af3cfb.dtsi

@@ -0,0 +1,11 @@
+
+/*
+ * Copyright (c) 2024 Piotr Rak <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define RA_SOC_PINS 144
+
+#include <renesas/ra/ra4mxxf-common-sp-flash-1MB.dtsi>
+#include <renesas/ra/ra4m-cm33-common.dtsi>

dts/arm/renesas/ra/ra4m-cm33-common.dtsi

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+#include <mem.h>
+#include <freq.h>
+#include <arm/armv8-m.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/renesas-ra-icu.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m33";
+			reg = <0>;
+		};
+	};
+
+	sram0: memory0@20000000 {
+		compatible = "mmio-sram";
+                reg = <0x20000000 DT_SIZE_K(128)>;
+        };
+
+        soc {
+		interrupt-parent = <&icu>;
+		icu: interrupt-controller@40006000 {
+			compatible = "renesas,ra-interrupt-controller-unit";
+			reg = <0x40006000 0x40>;
+			reg-names = "icu";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+
+		ioport0: gpio@40080000 {
+			compatible = "renesas,ra-gpio";
+			reg = <0x40080000 0x20>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+                        status = "disabled";
+                };
+
+		ioport4: gpio@40080080 {
+			compatible = "renesas,ra-gpio";
+			reg = <0x40080080 0x20>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+                        status = "disabled";
+                };
+
+
+		pinctrl: pinctrl@40080800 {
+			compatible = "renesas,ra-pinctrl";
+			reg = <0x40080800 0x500 0x40080d03 0x1>;
+			reg-names = "pfs", "pmisc_pwpr";
+			status = "okay";
+		};
+        };
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};

dts/arm/renesas/ra/ra4mxxf-common-sp-flash-1MB.dtsi

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+#include <mem.h>
+
+/ {
+        soc {
+		fcu: flash-controller@4001c100 {
+			compatible = "renesas,ra-flash-controller";
+                        reg = <0x4001c100 0x42>;
+                        reg-names = "fcache";
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+                        flash0: flash0@0 {
+				compatible = "soc-nv-flash";
+				reg = <0x00000000 DT_SIZE_K(1024)>;
+                        };
+                };
+	};
+};